| Presentation | 2015-12-02 A C Framework for Integrating Algorithm Description and CGRA Implementation Yasuhiko Nakashima, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We need high-speed, low-cost and low-power embedded computers for intelligent IoT devices. In contrast to vector accelerators and GPGPUs that inherently require high memory bandwidth for filling SIMD facilities, accelerators based on CGRA can show good performance under severe limitations on memory bandwidth. In usual, such hardware requires special programming language and elaborate tuning to get high performance. However, many programmers need easier way to write programs with long-life language such as C and to tune the speed. In this work, an integrated programming framework that regards reusability of source code as most important is demonstrated. C codes can be compiled for both traditional computers and CGRAs, and also be used for designing hardware with high-level-synthesis. Moreover, programmers can tune CGRA programs at assembly language level just using C, and can design customized CGRA by modifying C library. As a first step, proposed CGRA description is found to show favorable performance compared with original C source code. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | CGRA / C / Framework |
| Paper # | CPSY2015-65 |
| Date of Issue | 2015-11-24 (CPSY) |
| Conference Information | |
| Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
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| Conference Date | 2015/12/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A C Framework for Integrating Algorithm Description and CGRA Implementation |
| Sub Title (in English) | |
| Keyword(1) | CGRA |
| Keyword(2) | C |
| Keyword(3) | Framework |
| 1st Author's Name | Yasuhiko Nakashima |
| 1st Author's Affiliation | NARA Institute of Science and Technology(NAIST) |
| Date | 2015-12-02 |
| Paper # | CPSY2015-65 |
| Volume (vol) | vol.115 |
| Number (no) | CPSY-342 |
| Page | pp.pp.21-26(CPSY), |
| #Pages | 6 |
| Date of Issue | 2015-11-24 (CPSY) |