| Presentation | 2015-12-03 Exploration of Address Offsets of Basic Blocks for Cache Hit Ratio Improvement Junya Goto, Nagisa Ishiura, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This article proposes a method of reducing cache misses on an instruction memory by inserting offsets before basic blocks of a given program. The addresses of the basic blocks are adjusted by a unit smaller than the cache block size. A combination of the offsets that minimizes cache miss counts, which are computed by cache simulation, is searched. Since exhaustive search would require time exponential to the number of the offsets, the solution is searched by simulated annealing. An experiment on 7 benchmarks, assuming a single-level direct-mapping instruction cache, resulted in about 10% reduction in the cache miss count on average. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | cache memory / simulated annealing / offset / cache miss rate / basic block |
| Paper # | VLD2015-74,DC2015-70 |
| Date of Issue | 2015-11-24 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
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| Conference Date | 2015/12/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Exploration of Address Offsets of Basic Blocks for Cache Hit Ratio Improvement |
| Sub Title (in English) | |
| Keyword(1) | cache memory |
| Keyword(2) | simulated annealing |
| Keyword(3) | offset |
| Keyword(4) | cache miss rate |
| Keyword(5) | basic block |
| 1st Author's Name | Junya Goto |
| 1st Author's Affiliation | KWANSEI GAKUIN University(K.G.) |
| 2nd Author's Name | Nagisa Ishiura |
| 2nd Author's Affiliation | KWANSEI GAKUIN University(K.G.) |
| Date | 2015-12-03 |
| Paper # | VLD2015-74,DC2015-70 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-338,DC-339 |
| Page | pp.pp.237-241(VLD), pp.237-241(DC), |
| #Pages | 5 |
| Date of Issue | 2015-11-24 (VLD, DC) |