| Presentation | 2015-12-02 The adaptive body bias generator for achieving the ultra-low power operation of the logic circuit Tomoaki Koide, Kouichirou Ishibashi, Nobuyuki Sugi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The leakage has been increasing by miniaturization of the transistor in recently year. Adaptive body bias generator with controlled threshold voltage and leakage current using 65nm SOTB (Silicon on Thin Buried oxide) CMOS process is present this paper. Using this propose circuit, the power consumption at the minimum operating point of the logic circuit was obtained by simulation to be reduced by up to 43.8%. In measurement, it was confirmed that it outputs a constant voltage in the power supply voltage 0.5V or more. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Body bias / Ultra-low power / SOTB process cmos |
| Paper # | CPM2015-134,ICD2015-59 |
| Date of Issue | 2015-11-24 (CPM, ICD) |
| Conference Information | |
| Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
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| Conference Date | 2015/12/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The adaptive body bias generator for achieving the ultra-low power operation of the logic circuit |
| Sub Title (in English) | |
| Keyword(1) | Body bias |
| Keyword(2) | Ultra-low power |
| Keyword(3) | SOTB process cmos |
| 1st Author's Name | Tomoaki Koide |
| 1st Author's Affiliation | The University of Electro-Communications(UEC) |
| 2nd Author's Name | Kouichirou Ishibashi |
| 2nd Author's Affiliation | The University of Electro-Communications(UEC) |
| 3rd Author's Name | Nobuyuki Sugi |
| 3rd Author's Affiliation | Low Power Electronics Association & Project(LEAP) |
| Date | 2015-12-02 |
| Paper # | CPM2015-134,ICD2015-59 |
| Volume (vol) | vol.115 |
| Number (no) | CPM-340,ICD-341 |
| Page | pp.pp.39-43(CPM), pp.39-43(ICD), |
| #Pages | 5 |
| Date of Issue | 2015-11-24 (CPM, ICD) |