| Presentation | 2015-12-03 An approach to LFSR/MISR seed generation for delay fault BIST Daichi Shimazu, Satishi Ohtake, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a method of LFSR/MISR seed generation for delay fault BIST. A widely used conventional way to generate seeds is the following: a test cube for a fault is first generated and the cube is then converted into a seed. However, the conversion does not always succeed and the fault may not be detected. The authors' group has proposed an LFSR seed generation method for scan based BIST which aims to detect delay faults using ATPG with the launch-off-capture (LoC) scheme. This approach models dependency between an LFSR seed and the value of scan FFs in a combinational circuit called an XOR network and connects it to the CUT as a constraint of ATPG. The model enables direct seed generation by using ATPG. In this paper, an XOR network supporting LFSR and MISR for delay fault testing is designed and used for direct seed generation. Experiments using ITC'99 and IWLS'05 benchmark circuits are performed to evaluate the effectiveness of the proposed method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | BIST / seed generation / LFSR/MISR / delay fault / constrained test generation |
| Paper # | VLD2015-70,DC2015-66 |
| Date of Issue | 2015-11-24 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
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| Conference Date | 2015/12/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An approach to LFSR/MISR seed generation for delay fault BIST |
| Sub Title (in English) | |
| Keyword(1) | BIST |
| Keyword(2) | seed generation |
| Keyword(3) | LFSR/MISR |
| Keyword(4) | delay fault |
| Keyword(5) | constrained test generation |
| 1st Author's Name | Daichi Shimazu |
| 1st Author's Affiliation | Oita University(Oita Univ.) |
| 2nd Author's Name | Satishi Ohtake |
| 2nd Author's Affiliation | Oita University(Oita Univ.) |
| Date | 2015-12-03 |
| Paper # | VLD2015-70,DC2015-66 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-338,DC-339 |
| Page | pp.pp.213-218(VLD), pp.213-218(DC), |
| #Pages | 6 |
| Date of Issue | 2015-11-24 (VLD, DC) |