| Presentation | 2015-12-02 A Design of a Quick-Lock All-Digital CDR with Improved Jitter Performance by Fractional Phase Selection Technique Norihito Tohge, Tetsuya Iizuka, Toru Nakura, Satoshi Miura, Yoshimichi Murakami, Kunihiro Asada, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A quick-lock all-digital Clock-Data Recovery circuit that does not require a reference clock is propposed. InternalTime-to-Digital Converter and Phase Selector share a set of inverter-based delay lines and that enables quick frequency lockingby using few bits of preamble signal. This CDR circuit is composed of standard-cell-based digital circuit and does not consumedynamic power in its stand-by phase. Therefore, the proposed circuit is suitable especially for Internet-of-Everything applicationsthat work intemittently and demand small power consumption. In this design, newly-proposed fractional-phase-selectiontechnique is introduced to ameliorate its jitter tolerance. A proof-of-concept design is implemented in a 65 nm FD-SOI processand verified by simulations. The circuit works from 1.2 to 2.3 Gbps and consumes 22.3mW at 2.3 Gbps while occupying0.21mm2. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Clock-Data Recovery / Burst-Mode CDR / Refelence-Less / All-Digital |
| Paper # | CPM2015-130,ICD2015-55 |
| Date of Issue | 2015-11-24 (CPM, ICD) |
| Conference Information | |
| Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
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| Conference Date | 2015/12/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Design of a Quick-Lock All-Digital CDR with Improved Jitter Performance by Fractional Phase Selection Technique |
| Sub Title (in English) | |
| Keyword(1) | Clock-Data Recovery |
| Keyword(2) | Burst-Mode CDR |
| Keyword(3) | Refelence-Less |
| Keyword(4) | All-Digital |
| Keyword(5) | |
| 1st Author's Name | Norihito Tohge |
| 1st Author's Affiliation | The University of Tokyo(Univ. of Tokyo) |
| 2nd Author's Name | Tetsuya Iizuka |
| 2nd Author's Affiliation | The University of Tokyo(Univ. of Tokyo) |
| 3rd Author's Name | Toru Nakura |
| 3rd Author's Affiliation | The University of Tokyo(Univ. of Tokyo) |
| 4th Author's Name | Satoshi Miura |
| 4th Author's Affiliation | THine Electronics, Inc.(THine) |
| 5th Author's Name | Yoshimichi Murakami |
| 5th Author's Affiliation | THine Electronics, Inc.(THine) |
| 6th Author's Name | Kunihiro Asada |
| 6th Author's Affiliation | The University of Tokyo(Univ. of Tokyo) |
| Date | 2015-12-02 |
| Paper # | CPM2015-130,ICD2015-55 |
| Volume (vol) | vol.115 |
| Number (no) | CPM-340,ICD-341 |
| Page | pp.pp.17-22(CPM), pp.17-22(ICD), |
| #Pages | 6 |
| Date of Issue | 2015-11-24 (CPM, ICD) |