| Presentation | 2015-12-03 Cache Energy Reduction by Switching between L1 High Power and Low Power Cache under DVFS Environment Kaoru Saito, Ryotaro Kobayashi, Hajime Shimada, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Current CPU utilizes cache memory for decreasing an access speed gap between CPU and main memory. But the cache occupies a large part of the processor energy consumption. Furthermore, due to SRAM characteristic, cache cannot reduce supply voltage compared to CPU core so that DVFS cannot reduce much cache energy. So, we thought that we can reduce further cache energy consumption by preparing different power and speed design cache and switches them in proportion to DVFS activity. Our proposal reduces energy by modifying cache hierarchy to prioritizing low-power and low-speed cache in proportion to DVFS activity. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Cache Energy Consumption Reduction / DVFS / Cache Memory / L1 High Power/Low Power Cache |
| Paper # | CPSY2015-72 |
| Date of Issue | 2015-11-24 (CPSY) |
| Conference Information | |
| Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
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| Conference Date | 2015/12/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Cache Energy Reduction by Switching between L1 High Power and Low Power Cache under DVFS Environment |
| Sub Title (in English) | |
| Keyword(1) | Cache Energy Consumption Reduction |
| Keyword(2) | DVFS |
| Keyword(3) | Cache Memory |
| Keyword(4) | L1 High Power/Low Power Cache |
| 1st Author's Name | Kaoru Saito |
| 1st Author's Affiliation | Toyohashi University of Technology(Toyohashi Univ of Tech) |
| 2nd Author's Name | Ryotaro Kobayashi |
| 2nd Author's Affiliation | Toyohashi University of Technology(Toyohashi Univ of Tech) |
| 3rd Author's Name | Hajime Shimada |
| 3rd Author's Affiliation | Nagoya University(Nagoya Univ.) |
| Date | 2015-12-03 |
| Paper # | CPSY2015-72 |
| Volume (vol) | vol.115 |
| Number (no) | CPSY-342 |
| Page | pp.pp.63-68(CPSY), |
| #Pages | 6 |
| Date of Issue | 2015-11-24 (CPSY) |