Presentation | 2015-12-02 A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa, |
---|---|
PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | With recent process scaling in FPGAs, interconnection delays and clock skews have a large impact on the latency of a circuit and then may degrade operation frequency. We must consider interconnection delays and clock skews in floorplan-aware FPGA-HLS flow to design circuits having small latency. In this paper, we propose a floorplan-aware high-level synthesis algorithm for FPGA designs optimizing operation frequency of a circuit by improving interconnection delays and clock skews on the critical-path. Our target architecture is HDR, one of distributed-register architectures, and then we can consider module floorplan easily. Based on it, we estimate the delay of each signal path including interconnection delays and clock-skews, and identify the critical-path. To optimize them, we propose a novel scheduling/FU binding method and a novel floorplanning method. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the latency by up to 24% compared with conventional approaches. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | high-level synthesis (HLS) / FPGA / clock skew / interconnection delay / floorplan |
Paper # | VLD2015-54,DC2015-50 |
Date of Issue | 2015-11-24 (VLD, DC) |
Conference Information | |
Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
---|---|
Conference Date | 2015/12/1(3days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | Nagasaki Kinro Fukushi Kaikan |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
Paper Information | |
Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
---|---|
Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs |
Sub Title (in English) | |
Keyword(1) | high-level synthesis (HLS) |
Keyword(2) | FPGA |
Keyword(3) | clock skew |
Keyword(4) | interconnection delay |
Keyword(5) | floorplan |
1st Author's Name | Koichi Fujiwara |
1st Author's Affiliation | Waseda University(Waseda Univ.) |
2nd Author's Name | kazushi Kawamura |
2nd Author's Affiliation | Waseda University(Waseda Univ.) |
3rd Author's Name | Masao Yanagisawa |
3rd Author's Affiliation | Waseda University(Waseda Univ.) |
4th Author's Name | Nozomu Togawa |
4th Author's Affiliation | Waseda University(Waseda Univ.) |
Date | 2015-12-02 |
Paper # | VLD2015-54,DC2015-50 |
Volume (vol) | vol.115 |
Number (no) | VLD-338,DC-339 |
Page | pp.pp.99-104(VLD), pp.99-104(DC), |
#Pages | 6 |
Date of Issue | 2015-11-24 (VLD, DC) |