| Presentation | 2015-12-02 Formulation to SAT for Acceleration in 1D Layout Area Minimization of CMOS circuits Hayato Mashiko, Yukihide Kohira, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In layout design for LSI circuits, the layout area is minimized to reduce the fabrication cost and to increase the yield of LSI chips. In this thesis, we focus on a 1D layout design of CMOS circuits, where the height can be fixed. In the 1D layout of CMOS circuits, the width minimization corresponds to the maximization of the number of shared diffusions and the height minimization corresponds to the minimization of the number of tracks. The 1D layout area minimization method using SAT solver has been proposed for CMOS circuits so that the number of shared diffusions is maximized with the minimum number of tracks. However, since the formulations of the constraints and the objective function to SAT are ineffective in the existing method, its computational time is long. In this research, we propose new formulations of constraints and an objective function to SAT for acceleration. To confirm the effectiveness of the proposed method, the experimental results between the existing method and the proposed method are compared. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | CMOS circuit / 1D layout / layout area minimization / SAT / acceleration |
| Paper # | VLD2015-51,DC2015-47 |
| Date of Issue | 2015-11-24 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
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| Conference Date | 2015/12/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Formulation to SAT for Acceleration in 1D Layout Area Minimization of CMOS circuits |
| Sub Title (in English) | |
| Keyword(1) | CMOS circuit |
| Keyword(2) | 1D layout |
| Keyword(3) | layout area minimization |
| Keyword(4) | SAT |
| Keyword(5) | acceleration |
| 1st Author's Name | Hayato Mashiko |
| 1st Author's Affiliation | The University of Aizu(Univ. of Aizu) |
| 2nd Author's Name | Yukihide Kohira |
| 2nd Author's Affiliation | The University of Aizu(Univ. of Aizu) |
| Date | 2015-12-02 |
| Paper # | VLD2015-51,DC2015-47 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-338,DC-339 |
| Page | pp.pp.81-86(VLD), pp.81-86(DC), |
| #Pages | 6 |
| Date of Issue | 2015-11-24 (VLD, DC) |