| Presentation | 2015-12-01 Background Sequence Generation for Neighborhood Pattern Sensitive Fault Testing in Random Access Memories Shin'ya Ueoka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The Neighborhood Pattern Sensitive Fault (NPSF) is widely discussed fault model for memories, and it occurs when a memory cell is influenced by a certain pattern of its neiborhood cells in the memory. The multi-background march test is one of test methods for NPSF, and it consists of several backgrounds and an operation sequence. However, the existing multi-background march tests are manually generated by experts to detect all NPSFs. The purpose of this paper is to reduce the test length of multi-background march test, and we present an automatic generation method of background sequence that removes redundant backgrounds by taking the relation between order of background and detected faults into account. Experimental results show that the proposed method can automatically generate the background pattern sequence for NPSF, and reaches high fault coverage under sequence length constraint. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Random access memory / Memory BIST / Neighborhood pattern sensitive fault / March test |
| Paper # | VLD2015-40,DC2015-36 |
| Date of Issue | 2015-11-24 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
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| Conference Date | 2015/12/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Background Sequence Generation for Neighborhood Pattern Sensitive Fault Testing in Random Access Memories |
| Sub Title (in English) | |
| Keyword(1) | Random access memory |
| Keyword(2) | Memory BIST |
| Keyword(3) | Neighborhood pattern sensitive fault |
| Keyword(4) | March test |
| 1st Author's Name | Shin'ya Ueoka |
| 1st Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 2nd Author's Name | Tomokazu Yoneda |
| 2nd Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 3rd Author's Name | Yuta Yamato |
| 3rd Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 4th Author's Name | Michiko Inoue |
| 4th Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| Date | 2015-12-01 |
| Paper # | VLD2015-40,DC2015-36 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-338,DC-339 |
| Page | pp.pp.19-24(VLD), pp.19-24(DC), |
| #Pages | 6 |
| Date of Issue | 2015-11-24 (VLD, DC) |