| Presentation | 2015-12-03 Implementation and Evaluation of Peak Current Reduction Bandpass Filter using Asynchronous Circuits Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In synchronous circuits, peak currents flow at a constant frequency since a global clock signal which is a timing signal activates storage elements in the whole chip. Electromagnetic waves with the constant frequency may occur in synchronous circuits due to the peak currents. As a result, several noises occur. As a circuit size increases, the influence of the noises becomes remarkable since peak currents increase. On the other hand, in asynchronous circuits, peak currents are flattened since timing signals perform based on the request-and-acknowledge handshaking protocol only when and where they are needed between registers. In this research, we implemented some asynchronous bandpass filter circuits using 130nm process technology which can reduce peak currents, instead of synchronous circuits which are commonly used now. Then, their performances including the noise characteristics are compared with those of synchronous bandpass filter circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Dependable Technology / Asynchronous Circuit / Filter Circuit / MOUSETRAP Circuit / HSPICE / Verilog |
| Paper # | VLD2015-68,DC2015-64 |
| Date of Issue | 2015-11-24 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
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| Conference Date | 2015/12/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation and Evaluation of Peak Current Reduction Bandpass Filter using Asynchronous Circuits |
| Sub Title (in English) | |
| Keyword(1) | Dependable Technology |
| Keyword(2) | Asynchronous Circuit |
| Keyword(3) | Filter Circuit |
| Keyword(4) | MOUSETRAP Circuit |
| Keyword(5) | HSPICE |
| Keyword(6) | Verilog |
| 1st Author's Name | Tatsuya Ishikawa |
| 1st Author's Affiliation | Hirosaki University(Hirosaki Univ.) |
| 2nd Author's Name | Atsushi Kurokawa |
| 2nd Author's Affiliation | Hirosaki University(Hirosaki Univ.) |
| 3rd Author's Name | Masashi Imai |
| 3rd Author's Affiliation | Hirosaki University(Hirosaki Univ.) |
| Date | 2015-12-03 |
| Paper # | VLD2015-68,DC2015-64 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-338,DC-339 |
| Page | pp.pp.195-200(VLD), pp.195-200(DC), |
| #Pages | 6 |
| Date of Issue | 2015-11-24 (VLD, DC) |