| Presentation | 2015-12-03 Evaluation of Low-Voltage Characteristics of QDI model based Asynchronous VLSI Ryuhei Tachika, Atsushi Kurokawa, Masashi Imai, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In synchronous circuits, it is needed to distribute an identical clock signal to the whole chip with a constant frequency. On the other hand, asynchronous circuits independently perform only when and where they are needed thanks to preparing timing signals per each element. As a result, they can achieve low power consumption and high dependability. In this research, asynchronous adder circuits and synchronous adder circuits are designed and compared using the 28nm process technology. Then, the advantages of asynchronous circuits under low-voltage environments are quantitatively evaluated by measurement of signal waves and shmoo plots. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | QDImodel / HSPICE / shmooplot / asynchronous / synchronous / VLSI / C-element |
| Paper # | VLD2015-67,DC2015-63 |
| Date of Issue | 2015-11-24 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
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| Conference Date | 2015/12/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of Low-Voltage Characteristics of QDI model based Asynchronous VLSI |
| Sub Title (in English) | |
| Keyword(1) | QDImodel |
| Keyword(2) | HSPICE |
| Keyword(3) | shmooplot |
| Keyword(4) | asynchronous |
| Keyword(5) | synchronous |
| Keyword(6) | VLSI |
| Keyword(7) | C-element |
| 1st Author's Name | Ryuhei Tachika |
| 1st Author's Affiliation | Hirosaki University(Hirosaki Univ.) |
| 2nd Author's Name | Atsushi Kurokawa |
| 2nd Author's Affiliation | Hirosaki University(Hirosaki Univ.) |
| 3rd Author's Name | Masashi Imai |
| 3rd Author's Affiliation | Hirosaki University(Hirosaki Univ.) |
| Date | 2015-12-03 |
| Paper # | VLD2015-67,DC2015-63 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-338,DC-339 |
| Page | pp.pp.189-194(VLD), pp.189-194(DC), |
| #Pages | 6 |
| Date of Issue | 2015-11-24 (VLD, DC) |