| Presentation | 2015-10-26 A Power-Efficient Memory Hierarchy Design for the 3D Integration Era Wataru Uno, Masayuki Sato, Ryusuke Egawa, Hiroaki Kobayashi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | 3D-stacked memories are expected to play key roles to realize high-performance and low-power computing systems. This paper examines various computing systems including a 3D-stacked main memory and two- or three-level cache hierarchies. From the evaluation results, it is observed that cache hierarchy has an impact on the power efficiency of the memory subsystem with a 3D-stacked main memory. In addition, to judge the effectiveness of the L3 cache in improving power efficiency of the computing system including a 3D-stacked main memory, this paper examines two metrics of application characteristics, Miss Per Kilo-Instruction (MPKI) on the L2 caches and an MPKI reduction rate by employing the L3 cache. These metrics have potentials to clarify the best configuration of cache hierarchy that can maximize power efficiency of the computing system including a 3D-stacked main memory. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | stacked memory / 3D-IC / memory hierarchy / memory system / cache / computing system / computer architecture |
| Paper # | VLD2015-30,ICD2015-43,IE2015-65 |
| Date of Issue | 2015-10-19 (VLD, ICD, IE) |
| Conference Information | |
| Committee | ICD / IE / VLD / IPSJ-SLDM |
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| Conference Date | 2015/10/26(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Minoru Fujishima(Hiroshima Univ.) / Seishi Takamura(NTT) / Yusuke Matsunaga(Kyushu Univ.) / Masahiro Fukui(Ritsumeikan Univ.) |
| Vice Chair | Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Atsuro Ichigaya(NHK) / Takashi Takenana(NEC) |
| Secretary | Hideto Hidaka(Hiroshima Univ.) / Takayuki Hamamoto(NTT) / Atsuro Ichigaya(Chiba Inst. of Tech.) / Takashi Takenana(Ritsumeikan Univ.) / (Fujitsu Labs.) |
| Assistant | Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Keita Takahashi(Nagoya Univ.) / Kei Kawamura(KDDI R&D Labs.) / Ittetsu Taniguchi(Ritsumeikan Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Technical Committee on VLSI Design Technologies / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Power-Efficient Memory Hierarchy Design for the 3D Integration Era |
| Sub Title (in English) | |
| Keyword(1) | stacked memory |
| Keyword(2) | 3D-IC |
| Keyword(3) | memory hierarchy |
| Keyword(4) | memory system |
| Keyword(5) | cache |
| Keyword(6) | computing system |
| Keyword(7) | computer architecture |
| 1st Author's Name | Wataru Uno |
| 1st Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 2nd Author's Name | Masayuki Sato |
| 2nd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 3rd Author's Name | Ryusuke Egawa |
| 3rd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 4th Author's Name | Hiroaki Kobayashi |
| 4th Author's Affiliation | Tohoku University(Tohoku Univ.) |
| Date | 2015-10-26 |
| Paper # | VLD2015-30,ICD2015-43,IE2015-65 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-270,ICD-271,IE-272 |
| Page | pp.pp.19-24(VLD), pp.19-24(ICD), pp.19-24(IE), |
| #Pages | 6 |
| Date of Issue | 2015-10-19 (VLD, ICD, IE) |