| Presentation | 2015-10-29 Electrical Properties of MOSFETs Introducing Atomically Flat Gate Insulator/Silicon Interface Tetsuya Goto, Rihito Kuroda, Tomoyuki Suwa, Akinobu Teramoto, Toshiki Obara, Daiki Kimoto, Shigetoshi Sugawa, Yutaka Kamata, Yuki Kumagai, Katsuhiko Shibusawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Atomically flattening technology was introduced to the widely-used complementary metal oxide silicon (CMOS) process employing sallow trench isolation (STI) with 0.22 um technology. To obtain atomically flat Si surface for the wafer where device-isolation SiO2 film and Si coexist, both the reaction of Si with SiO2 and the etching of Si by residue gases of O2 and/or H2O should be suppressed. To realize this, the low-temperature atomically flattening technology was introduced using the developed ultraclean furnace where O2 and H2O residue gases can be reduced down to less than 30 ppb in Ar ambience. In addition, the gate oxide film was formed by the radical oxidation using the microwave excited Kr/O2 plasma to preserve atomic flatness at the gate insluator/Si interface. As a result, CMOSFETs having atomically flat gate insulator/Si interface were realized. The developed test array circuit was fabricated to statistically evaluate electrical characteristics of a very large number of MOSFETs in a short period of time. Thanks to the introduction of the atomically flat interface, gate source voltage noise amplitude originated from the random telegraph noise was reduced in nMOSFETs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Atomically Flat Si / Shallow Trench Isolation / Random Telegraph Noise |
| Paper # | SDM2015-74 |
| Date of Issue | 2015-10-22 (SDM) |
| Conference Information | |
| Committee | SDM |
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| Conference Date | 2015/10/29(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Niche, Tohoku Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Process Science and New Process Technology |
| Chair | Yuzou Oono(Univ. of Tsukuba) |
| Vice Chair | Tatsuya Kunikiyo(Renesas) |
| Secretary | Tatsuya Kunikiyo(Tohoku Univ.) |
| Assistant | Tadashi Yamaguchi(Renesas) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials |
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| Language | ENG-JTITLE |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Electrical Properties of MOSFETs Introducing Atomically Flat Gate Insulator/Silicon Interface |
| Sub Title (in English) | |
| Keyword(1) | Atomically Flat Si |
| Keyword(2) | Shallow Trench Isolation |
| Keyword(3) | Random Telegraph Noise |
| 1st Author's Name | Tetsuya Goto |
| 1st Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 2nd Author's Name | Rihito Kuroda |
| 2nd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 3rd Author's Name | Tomoyuki Suwa |
| 3rd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 4th Author's Name | Akinobu Teramoto |
| 4th Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 5th Author's Name | Toshiki Obara |
| 5th Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 6th Author's Name | Daiki Kimoto |
| 6th Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 7th Author's Name | Shigetoshi Sugawa |
| 7th Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 8th Author's Name | Yutaka Kamata |
| 8th Author's Affiliation | LAPIS Semiconductor Miyagi Co., Ltd(LAPIS Semi. Miyagi) |
| 9th Author's Name | Yuki Kumagai |
| 9th Author's Affiliation | LAPIS Semiconductor Miyagi Co., Ltd(LAPIS Semi. Miyagi) |
| 10th Author's Name | Katsuhiko Shibusawa |
| 10th Author's Affiliation | LAPIS Semiconductor Miyagi Co., Ltd(LAPIS Semi. Miyagi) |
| Date | 2015-10-29 |
| Paper # | SDM2015-74 |
| Volume (vol) | vol.115 |
| Number (no) | SDM-280 |
| Page | pp.pp.17-22(SDM), |
| #Pages | 6 |
| Date of Issue | 2015-10-22 (SDM) |