Presentation 2015-10-26
Design of Fine-Resolution Pulse Shrinking Time-to-Digital Converter
Takehisa Koga, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A pulse-shrinking Time-to-Digital Converter (TDC) with an offset pulse width detection scheme is presented. In the conventional pulse-shrinking TDCs, the pulse-shrinking rate, which is defined as a pulse width change through a single pulse-shrinking buffer (PSB), is supposed to be constant. However, when the pulse width is narrow, the shrinking rate actually is not constant. This causes a non-linearity of TDCs. In order to avoid this issue, we propose an offset pulse detection scheme for the pulse-shrinking TDC that is composed of a ring of PSBs. The input time difference is converted to a pulse along with a fixed offset width. This pulse width keeps shrinking while it propagates on the PSB ring, then the conversion process finishes when the pulse width is shrunk below the original offset pulse width. If we chose a sufficient offset pulse width, the pulse shrinking rate remains constant during the time-to-digital conversion process. The proposed TDC is designed with 0.18$mu$m CMOS process and 3.8MS/s, 1.8ps time resolution with +1.3/-0.9LSB DNL and +2.5/-3.0LSB INL is verified by post-layout simulation. Its layout area and power consumption are 0.07mm$^2$ and 4.6mW, respectively.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) TDC / pulse-shrinking / buffer ring / offset / fine time resolution
Paper # VLD2015-29,ICD2015-42,IE2015-64
Date of Issue 2015-10-19 (VLD, ICD, IE)

Conference Information
Committee ICD / IE / VLD / IPSJ-SLDM
Conference Date 2015/10/26(2days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Minoru Fujishima(Hiroshima Univ.) / Seishi Takamura(NTT) / Yusuke Matsunaga(Kyushu Univ.) / Masahiro Fukui(Ritsumeikan Univ.)
Vice Chair Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Atsuro Ichigaya(NHK) / Takashi Takenana(NEC)
Secretary Hideto Hidaka(Hiroshima Univ.) / Takayuki Hamamoto(NTT) / Atsuro Ichigaya(Chiba Inst. of Tech.) / Takashi Takenana(Ritsumeikan Univ.) / (Fujitsu Labs.)
Assistant Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Keita Takahashi(Nagoya Univ.) / Kei Kawamura(KDDI R&D Labs.) / Ittetsu Taniguchi(Ritsumeikan Univ.)

Paper Information
Registration To Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Technical Committee on VLSI Design Technologies / Special Interest Group on System and LSI Design Methodology
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of Fine-Resolution Pulse Shrinking Time-to-Digital Converter
Sub Title (in English)
Keyword(1) TDC
Keyword(2) pulse-shrinking
Keyword(3) buffer ring
Keyword(4) offset
Keyword(5) fine time resolution
1st Author's Name Takehisa Koga
1st Author's Affiliation The University of Tokyo(Univ. of Tokyo)
2nd Author's Name Tetsuya Iizuka
2nd Author's Affiliation The University of Tokyo(Univ. of Tokyo)
3rd Author's Name Toru Nakura
3rd Author's Affiliation The University of Tokyo(Univ. of Tokyo)
4th Author's Name Kunihiro Asada
4th Author's Affiliation The University of Tokyo(Univ. of Tokyo)
Date 2015-10-26
Paper # VLD2015-29,ICD2015-42,IE2015-64
Volume (vol) vol.115
Number (no) VLD-270,ICD-271,IE-272
Page pp.pp.13-18(VLD), pp.13-18(ICD), pp.13-18(IE),
#Pages 6
Date of Issue 2015-10-19 (VLD, ICD, IE)