| Presentation | 2015-08-04 Design Space Exploration of Computational Photography Accelerator Yuttakon Yuttakonkit, Tran Thi Hong, Shinya Takamaeda, Yasuhiko Nakashima, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Computational photography applications use image processing to extract quality improvement or addi- tional features. Instances of current implementation are refocusing and post-made depth of field for smartphones, optical manufacturing inspection for industrial. One key property of these applications is obtaining depth of objects from still image. Instead of using multiple cameras, a single 4D image that consists of collated micro images can directly extract the depth of objects by differentiating amongst multiple micro images. Though calculations inside a micro image is capable for parallelism but the far distance between comparison pair’s pixel on neighbor micro image is drastically obstruction. This Sparse Stencil memory access is the most hotspot for 4D image application’s algorithm. Recent mobile device especially smartphone also try to add 4D like’s features but obstructed with pro- cessing performance and also power consumption due to limited battery, thus either quality or resolution is too low. To overcome this, we proposed an accelerator, which operate along side with the main mobile processor. The appli- cations’s algorithm are analyzed, then we use conventional multicore processor simulator to conduct design space exploration. Result shows that, speed of cache is dominated the performance while size of cache is least effective. ROB size and amount of cores is the second priority. Furthermore by comparing the simulation with real hardware result, we found that not only parameters tuning on subject architectures but detail on internal architecture design is also essential to improve both performance and power efficiency. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Architecture designSystem designComputational photographyStencil applicationMobile Processor |
| Paper # | CPSY2015-17 |
| Date of Issue | 2015-07-28 (CPSY) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-ARC |
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| Conference Date | 2015/8/4(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | B-Con Plaza (Beppu) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Parallel, Distributed and Cooperative Processing |
| Chair | Yasuhiko Nakashima(NAIST) / Nobuyasu Kanekawa(Hitachi) |
| Vice Chair | Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Michiko Inoue(NAIST) |
| Secretary | Koji Nakano(Fujitsu Labs.) / Hidetsugu Irie(NII) / Michiko Inoue(RTRI) / (Kyoto Sangyo Univ.) |
| Assistant | Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System Architecture |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design Space Exploration of Computational Photography Accelerator |
| Sub Title (in English) | |
| Keyword(1) | Architecture designSystem designComputational photographyStencil applicationMobile Processor |
| 1st Author's Name | Yuttakon Yuttakonkit |
| 1st Author's Affiliation | Nara Institute of Science and Techonology(NAIST) |
| 2nd Author's Name | Tran Thi Hong |
| 2nd Author's Affiliation | Nara Institute of Science and Techonology(NAIST) |
| 3rd Author's Name | Shinya Takamaeda |
| 3rd Author's Affiliation | Nara Institute of Science and Techonology(NAIST) |
| 4th Author's Name | Yasuhiko Nakashima |
| 4th Author's Affiliation | Nara Institute of Science and Techonology(NAIST) |
| Date | 2015-08-04 |
| Paper # | CPSY2015-17 |
| Volume (vol) | vol.115 |
| Number (no) | CPSY-174 |
| Page | pp.pp.7-12(CPSY), |
| #Pages | 6 |
| Date of Issue | 2015-07-28 (CPSY) |