| Presentation | 2015-08-04 The Network-on-Chip Optimization By Using Of Genetic Algorithm Daichi Murakami, Kei Hiraki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Hetero-NoC is a new design of Network-on-Chip (NoC) which achieves lower latency without increasing the amount of resources. In Hetero-NoC's design, two different sizes of components should be arranged properly. Previous arrangements, however, depend on thecenter-oriented traffic property which is seen in only simple NoC, so it is suspicious that these arrangements could benefit the real NoC which is often more complex. In addition, the method of designing Hetero-NoC from its qualitative aspects is not formalized yet and predicated to be difficult because of many factors in NoC like the location of memory controller, routing algorithm, and so on. In this research, we optimized the arrangements of the NoC's components by using of NoC simulation and genetic algorithm. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | NoC / Hetero-NoC / Genetic Algorithm / Optimization |
| Paper # | CPSY2015-16 |
| Date of Issue | 2015-07-28 (CPSY) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-ARC |
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| Conference Date | 2015/8/4(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | B-Con Plaza (Beppu) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Parallel, Distributed and Cooperative Processing |
| Chair | Yasuhiko Nakashima(NAIST) / Nobuyasu Kanekawa(Hitachi) |
| Vice Chair | Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Michiko Inoue(NAIST) |
| Secretary | Koji Nakano(Fujitsu Labs.) / Hidetsugu Irie(NII) / Michiko Inoue(RTRI) / (Kyoto Sangyo Univ.) |
| Assistant | Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The Network-on-Chip Optimization By Using Of Genetic Algorithm |
| Sub Title (in English) | |
| Keyword(1) | NoC |
| Keyword(2) | Hetero-NoC |
| Keyword(3) | Genetic Algorithm |
| Keyword(4) | Optimization |
| 1st Author's Name | Daichi Murakami |
| 1st Author's Affiliation | The University of Tokyo(UTokyo) |
| 2nd Author's Name | Kei Hiraki |
| 2nd Author's Affiliation | The University of Tokyo(UTokyo) |
| Date | 2015-08-04 |
| Paper # | CPSY2015-16 |
| Volume (vol) | vol.115 |
| Number (no) | CPSY-174 |
| Page | pp.pp.1-6(CPSY), |
| #Pages | 6 |
| Date of Issue | 2015-07-28 (CPSY) |