| Presentation | 2015-08-04 A Feasibility Study on Implementing Micro-ITRON Task Scheduler by Wired-logic Kouichi Araki, Tomoaki Ukezono, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Software overheads which are caused by task scheduler inside operating systems have possibility of fluctuation. It impairs accuracy in approximation of completion time for individual task, and it might make real-time performance worse on embedded systems. On the other hand, until now, integration degree of transistor has continued to increase by build-out of recent fine processing technology. Consequently, this paper considers how scale of task scheduler can be achieved using wired-logic by the recent fine processing technology as an example for micro-ITRON task schedulers. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Task Scheduler / Wired-logic / Micro-ITRON |
| Paper # | CPSY2015-20 |
| Date of Issue | 2015-07-28 (CPSY) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-ARC |
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| Conference Date | 2015/8/4(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | B-Con Plaza (Beppu) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Parallel, Distributed and Cooperative Processing |
| Chair | Yasuhiko Nakashima(NAIST) / Nobuyasu Kanekawa(Hitachi) |
| Vice Chair | Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Michiko Inoue(NAIST) |
| Secretary | Koji Nakano(Fujitsu Labs.) / Hidetsugu Irie(NII) / Michiko Inoue(RTRI) / (Kyoto Sangyo Univ.) |
| Assistant | Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Feasibility Study on Implementing Micro-ITRON Task Scheduler by Wired-logic |
| Sub Title (in English) | |
| Keyword(1) | Task Scheduler |
| Keyword(2) | Wired-logic |
| Keyword(3) | Micro-ITRON |
| 1st Author's Name | Kouichi Araki |
| 1st Author's Affiliation | Godai Kaihatsu Corporation(Godai Kaihatsu) |
| 2nd Author's Name | Tomoaki Ukezono |
| 2nd Author's Affiliation | Fukuoka University(Fukuoka Univ.) |
| Date | 2015-08-04 |
| Paper # | CPSY2015-20 |
| Volume (vol) | vol.115 |
| Number (no) | CPSY-174 |
| Page | pp.pp.53-58(CPSY), |
| #Pages | 6 |
| Date of Issue | 2015-07-28 (CPSY) |