Presentation 2015-06-16
Performance Evaluation of Dependability Improvement Methods for Multiple Core Systems based on Markov Models
Masashi Imai, Tomohiro Yoneda,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) In embedded systems, multiple core system is a promising architecture not only for performance improvement, but also for dependability. Several dependability improvement methods have been presented. In this paper, three methods which contain the lock-step pair scheme, the TMR-spare scheme, and the proposed DTTR (Duplication with Temporary TMR and Reconfiguration) scheme are modeled using Markov chains. They are evaluated and compared in terms of the average failure rate.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Duplicated task execution / Temporal TMR execution / Reconfiguration / Markov model
Paper # DC2015-20
Date of Issue 2015-06-09 (DC)

Conference Information
Committee DC
Conference Date 2015/6/16(1days)
Place (in Japanese) (See Japanese page)
Place (in English) Kikai-Shinko-Kaikan Bldg.
Topics (in Japanese) (See Japanese page)
Topics (in English) Reliable design and Test, etc.
Chair Nobuyasu Kanekawa(Hitachi)
Vice Chair Michiko Inoue(NAIST)
Secretary Michiko Inoue(RTRI)
Assistant

Paper Information
Registration To Technical Committee on Dependable Computing
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Performance Evaluation of Dependability Improvement Methods for Multiple Core Systems based on Markov Models
Sub Title (in English)
Keyword(1) Duplicated task execution
Keyword(2) Temporal TMR execution
Keyword(3) Reconfiguration
Keyword(4) Markov model
1st Author's Name Masashi Imai
1st Author's Affiliation Hirosaki University(Hirosaki Univ.)
2nd Author's Name Tomohiro Yoneda
2nd Author's Affiliation National Institute of Informatics(NII)
Date 2015-06-16
Paper # DC2015-20
Volume (vol) vol.115
Number (no) DC-86
Page pp.pp.25-30(DC),
#Pages 6
Date of Issue 2015-06-09 (DC)