| Presentation | 2015-06-17 Accelerating techniques for test pattern compaction for large circuits Yusuke Matsunaga, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents accelerating techniques for test pattern compaction algorithm applicable for large scale circuits. New concepts called `sufficient assignments' and `mandatory assignments' for fault detection are proposed. Novel algorithms checking fault dominance and fault compatibility utilizing these concepts are also described. The experimental results show that the proposed techniques achieve big speed up while maintainig the test compaction capability similar. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | test pattern generation / test pattern compaction / SAT |
| Paper # | CAS2015-5,VLD2015-12,SIP2015-36,MSS2015-5 |
| Date of Issue | 2015-06-10 (CAS, VLD, SIP, MSS) |
| Conference Information | |
| Committee | MSS / CAS / SIP / VLD |
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| Conference Date | 2015/6/17(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Otaru University of Commerce |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System, signal processing and related topics |
| Chair | Satoshi Yamane(Kanazawa Univ.) / Satoshi Tanaka(Murata) / Osamu Houshuyama(NEC) / Yusuke Matsunaga(Kyushu Univ.) |
| Vice Chair | Morikazu Nakamura(Univ. of Ryukyus) / Toshihiko Takahashi(Niigata Univ.) / Makoto Nakashizuka(Chiba Inst. of Tech.) / Masahiro Okuda(Univ. of Kitakyushu) / Takashi Takenana(NEC) |
| Secretary | Morikazu Nakamura(Yamaguchi Univ.) / Toshihiko Takahashi(Toshiba) / Makoto Nakashizuka(Hitachi) / Masahiro Okuda(Tohoku Univ.) / Takashi Takenana(NEC) |
| Assistant | Hideki Kinjo(Okinawa Univ.) / Toshihiro Tachibana(Shonan Inst. of Tech.) / Yohei Nakamura(Hitachi) / Takamichi Miyata(Chiba Inst. of Tech.) / Ittetsu Taniguchi(Ritsumeikan Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Mathematical Systems Science and its applications / Technical Committee on Circuits and Systems / Technical Committee on Signal Processing / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Accelerating techniques for test pattern compaction for large circuits |
| Sub Title (in English) | |
| Keyword(1) | test pattern generation |
| Keyword(2) | test pattern compaction |
| Keyword(3) | SAT |
| 1st Author's Name | Yusuke Matsunaga |
| 1st Author's Affiliation | Kyushu University(Kyushu Univ.) |
| Date | 2015-06-17 |
| Paper # | CAS2015-5,VLD2015-12,SIP2015-36,MSS2015-5 |
| Volume (vol) | vol.115 |
| Number (no) | CAS-87,VLD-88,SIP-89,MSS-90 |
| Page | pp.pp.25-30(CAS), pp.25-30(VLD), pp.25-30(SIP), pp.25-30(MSS), |
| #Pages | 6 |
| Date of Issue | 2015-06-10 (CAS, VLD, SIP, MSS) |