| Presentation | 2015-06-16 A test data reduction method based on scan slice on BAST Makoto Nishikiori, Hiroshi Yamazaki, Toshinori Hosokawa, Masayuki Arai, Masayoshi Yoshimura, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | BAST is one of techniques to reduce the amount of test data while maintaining high test quality by combining built-in self test with deterministic test generation. On BAST architecture, a bit-flipping technique is used to convert pseudo-random patterns to deterministic patterns. The test data on BAST are consists of bit-flipping instructions and shift instructions. The number of bit-flipping instructions depends on that of conflicted bits between deterministic patterns and pseudo random patterns. Therefore, the number of conflicted bits must be reduced to decrease the amount of test data. In this paper, we focus that the number of the conflicted bits has variation at each scan slice. We propose a method to reduce the number of conflicted bits by applying an all bit-flipping instruction to scan slices with many conflicted bits. Experimental results show that the proposed method was effective to reduce the number of bit-flipping instructions and the amount of test data for ISCAS'89 and ITC'99 benchmark circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | BAST architecture / scan slice / BAST code / bit-flipping instructions |
| Paper # | DC2015-16 |
| Date of Issue | 2015-06-09 (DC) |
| Conference Information | |
| Committee | DC |
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| Conference Date | 2015/6/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reliable design and Test, etc. |
| Chair | Nobuyasu Kanekawa(Hitachi) |
| Vice Chair | Michiko Inoue(NAIST) |
| Secretary | Michiko Inoue(RTRI) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A test data reduction method based on scan slice on BAST |
| Sub Title (in English) | |
| Keyword(1) | BAST architecture |
| Keyword(2) | scan slice |
| Keyword(3) | BAST code |
| Keyword(4) | bit-flipping instructions |
| 1st Author's Name | Makoto Nishikiori |
| 1st Author's Affiliation | Nihon University(Nihon Univ.) |
| 2nd Author's Name | Hiroshi Yamazaki |
| 2nd Author's Affiliation | Nihon University(Nihon Univ.) |
| 3rd Author's Name | Toshinori Hosokawa |
| 3rd Author's Affiliation | Nihon University(Nihon Univ.) |
| 4th Author's Name | Masayuki Arai |
| 4th Author's Affiliation | Nihon University(Nihon Univ.) |
| 5th Author's Name | Masayoshi Yoshimura |
| 5th Author's Affiliation | Kyoto Sangyo University(Kyoto Sangyo Univ.) |
| Date | 2015-06-16 |
| Paper # | DC2015-16 |
| Volume (vol) | vol.115 |
| Number (no) | DC-86 |
| Page | pp.pp.1-6(DC), |
| #Pages | 6 |
| Date of Issue | 2015-06-09 (DC) |