| Presentation | 2015-06-19 An Area Optimization of 3D FPGA with high speed inter-layer communication link Yuto Takeuchi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the large scale integration (LSI) rather than miniaturization. However, because the through-silicon-via (TSV) of the vertical connection has a large area overhead, it is necessary to reduce the quantity of vertical routing resources that heavily required by the field-programmable gate array (FPGA). In this paper, we first create a face-down stacked FPGA by dividing routing and logic resources into different layers. Then, in order to minimize the number of TSVs and improve integration, face-down stacked FPGAs are connected by high speed serial links. The evaluation on the proposed 3D FPGA is performed with an area-minimized circuit partitioning method. Results show that a four layers 3D FPGA has a 10.78% slower delay while 70.21% smaller area than a 2D FPGA on average. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 3D-FPGA / High speed serial communication / TSV |
| Paper # | RECONF2015-4 |
| Date of Issue | 2015-06-12 (RECONF) |
| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2015/6/19(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kyoto University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | the 10th anniversary celebration of RECONF: Reconfigurable Systems, etc. |
| Chair | Minoru Watanabe(Shizuoka Univ.) |
| Vice Chair | Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) |
| Secretary | Masato Motomura(Toshiba) / Yuichiro Shibata(Univ. of Tsukuba) |
| Assistant | Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Area Optimization of 3D FPGA with high speed inter-layer communication link |
| Sub Title (in English) | |
| Keyword(1) | 3D-FPGA |
| Keyword(2) | High speed serial communication |
| Keyword(3) | TSV |
| Keyword(4) | |
| 1st Author's Name | Yuto Takeuchi |
| 1st Author's Affiliation | Kumamoto University(Kumamoto Univ) |
| 2nd Author's Name | Qian Zhao |
| 2nd Author's Affiliation | Kumamoto University(Kumamoto Univ) |
| 3rd Author's Name | Motoki Amagasaki |
| 3rd Author's Affiliation | Kumamoto University(Kumamoto Univ) |
| 4th Author's Name | Masahiro Iida |
| 4th Author's Affiliation | Kumamoto University(Kumamoto Univ) |
| 5th Author's Name | Morihiro Kuga |
| 5th Author's Affiliation | Kumamoto University(Kumamoto Univ) |
| 6th Author's Name | Toshinori Sueyoshi |
| 6th Author's Affiliation | Kumamoto University(Kumamoto Univ) |
| Date | 2015-06-19 |
| Paper # | RECONF2015-4 |
| Volume (vol) | vol.115 |
| Number (no) | RECONF-109 |
| Page | pp.pp.17-22(RECONF), |
| #Pages | 6 |
| Date of Issue | 2015-06-12 (RECONF) |