| Presentation | 2015-06-17 Extension of One-Instruction-Set Computer and Its Evaluation Noriaki Sakamoto, Tanvir Ahmed, Jason H. Anderson, Yuko Hara-Azumi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Subleq computer is one of the best-known Turing-Complete One-Instruction-Set Computers. Subleq instruction is a three-operand instruction, which performs subtraction of the first two operands followed by conditional jump depending on the subtraction result and the third operand. Its architecture is simple with small circuit area and expected to be realized even by post-silicon devices whose manufacturing yield is not high yet. However, Subleq is not efficient for certain types of instructions, including multiplication and right shift, which are frequently used in practical applications. In this paper, we propose an instruction set extension for Subleq by a simple instruction, such as bit-reversal subtraction, for reducing the execution cycle counts to perform multiplication and shift operations. We evaluate the effect on cycle count reduction as well as those on circuit area and clock frequency when implementing the extended Subleq computer on an FPGA. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Instruction-Set Architecture / One-Instruction-Set Computer / Subleq |
| Paper # | CAS2015-4,VLD2015-11,SIP2015-35,MSS2015-4 |
| Date of Issue | 2015-06-10 (CAS, VLD, SIP, MSS) |
| Conference Information | |
| Committee | MSS / CAS / SIP / VLD |
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| Conference Date | 2015/6/17(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Otaru University of Commerce |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System, signal processing and related topics |
| Chair | Satoshi Yamane(Kanazawa Univ.) / Satoshi Tanaka(Murata) / Osamu Houshuyama(NEC) / Yusuke Matsunaga(Kyushu Univ.) |
| Vice Chair | Morikazu Nakamura(Univ. of Ryukyus) / Toshihiko Takahashi(Niigata Univ.) / Makoto Nakashizuka(Chiba Inst. of Tech.) / Masahiro Okuda(Univ. of Kitakyushu) / Takashi Takenana(NEC) |
| Secretary | Morikazu Nakamura(Yamaguchi Univ.) / Toshihiko Takahashi(Toshiba) / Makoto Nakashizuka(Hitachi) / Masahiro Okuda(Tohoku Univ.) / Takashi Takenana(NEC) |
| Assistant | Hideki Kinjo(Okinawa Univ.) / Toshihiro Tachibana(Shonan Inst. of Tech.) / Yohei Nakamura(Hitachi) / Takamichi Miyata(Chiba Inst. of Tech.) / Ittetsu Taniguchi(Ritsumeikan Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Mathematical Systems Science and its applications / Technical Committee on Circuits and Systems / Technical Committee on Signal Processing / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Extension of One-Instruction-Set Computer and Its Evaluation |
| Sub Title (in English) | |
| Keyword(1) | Instruction-Set Architecture |
| Keyword(2) | One-Instruction-Set Computer |
| Keyword(3) | Subleq |
| 1st Author's Name | Noriaki Sakamoto |
| 1st Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 2nd Author's Name | Tanvir Ahmed |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 3rd Author's Name | Jason H. Anderson |
| 3rd Author's Affiliation | University of Toronto(Univ. of Toronto) |
| 4th Author's Name | Yuko Hara-Azumi |
| 4th Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| Date | 2015-06-17 |
| Paper # | CAS2015-4,VLD2015-11,SIP2015-35,MSS2015-4 |
| Volume (vol) | vol.115 |
| Number (no) | CAS-87,VLD-88,SIP-89,MSS-90 |
| Page | pp.pp.19-24(CAS), pp.19-24(VLD), pp.19-24(SIP), pp.19-24(MSS), |
| #Pages | 6 |
| Date of Issue | 2015-06-10 (CAS, VLD, SIP, MSS) |