| Presentation | 2015-06-20 A Rapid Verification Environment for Statistical Evaluation of PUF Circuits Toshihiro Katashita, Yasunori Onda, Yohei Hori, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this study, we constructed a rapid experimentation environment for Physically Unclonable Function (PUF) circuit verification. PUF is significant technology for device authentication, cryptographic key generation and countermeasure against counterfeits. In the field of PUF studies, FPGA is effective for evaluation and comparison between architectures. However, many devices are required to extract PUF parameters for evaluation. Thus, several FPGA boards were used. In this background, we developed an instrument and software that extracts PUF parameters from 120 FPGA devices automatically. In this paper, the structure and the procedure of testing are described, and the effectiveness is shown with preliminary experimentation using 100 devices. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Physical Unclonable Function (PUF) / Pseudo LFSR PUF / Arbiter PUF / FPGA / Verification Environment |
| Paper # | RECONF2015-18 |
| Date of Issue | 2015-06-12 (RECONF) |
| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2015/6/19(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kyoto University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | the 10th anniversary celebration of RECONF: Reconfigurable Systems, etc. |
| Chair | Minoru Watanabe(Shizuoka Univ.) |
| Vice Chair | Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) |
| Secretary | Masato Motomura(Toshiba) / Yuichiro Shibata(Univ. of Tsukuba) |
| Assistant | Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Rapid Verification Environment for Statistical Evaluation of PUF Circuits |
| Sub Title (in English) | |
| Keyword(1) | Physical Unclonable Function (PUF) |
| Keyword(2) | Pseudo LFSR PUF |
| Keyword(3) | Arbiter PUF |
| Keyword(4) | FPGA |
| Keyword(5) | Verification Environment |
| 1st Author's Name | Toshihiro Katashita |
| 1st Author's Affiliation | Advanced Industrial Science and Technology(AIST) |
| 2nd Author's Name | Yasunori Onda |
| 2nd Author's Affiliation | Advanced Industrial Science and Technology(AIST) |
| 3rd Author's Name | Yohei Hori |
| 3rd Author's Affiliation | Advanced Industrial Science and Technology(AIST) |
| Date | 2015-06-20 |
| Paper # | RECONF2015-18 |
| Volume (vol) | vol.115 |
| Number (no) | RECONF-109 |
| Page | pp.pp.97-102(RECONF), |
| #Pages | 6 |
| Date of Issue | 2015-06-12 (RECONF) |