Presentation 2015-06-08
Hardware Architecture of Generic Soft Cascaded Linear SVM Classifier
Eric Aliwarga, Jaehoon Yu, Masahide Hatanaka, Takao Onoye,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Support Vector Machine is renowned as a powerful machine learning algorithm for many classification problems. However, among all the works proposed for SVM hardware implementation, a lot of them are designed solely for specific purpose. This paper presents an SVM hardware architecture capable of classifying input data with arbitrary vector dimensionality and arbitrary precision, resulting in a generic support vector machine capable of classifying various targets. The proposed architecture also employs a speed-up method called soft cascade algorithm to enhance its performance. The results show that for CoHOG pedestrian detection, the proposed hardware architecture may classify up to 77 VGA images per second even under the condition that the architecture is not designed specifically for the mentioned purpose.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) support vector machinesoft cascadehardware architecture
Paper # SIS2015-6
Date of Issue 2015-06-01 (SIS)

Conference Information
Committee SIS
Conference Date 2015/6/8(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Arkas SASEBO
Topics (in Japanese) (See Japanese page)
Topics (in English) Smart Personal Systems, etc.
Chair Mitsuji Muneyasu(Kansai Univ.)
Vice Chair Hirokazu Tanaka(Toshiba) / Takayuki Nakachi(NTT)
Secretary Hirokazu Tanaka(Nagoya City Univ.) / Takayuki Nakachi(Toshiba)
Assistant Hiroyuki Tsuji(Kanagawa Inst. of Tech.) / Hakaru Tamukoh(Kyushu Inst. of Tech.)

Paper Information
Registration To Technical Committee on Smart Info-Media System
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Hardware Architecture of Generic Soft Cascaded Linear SVM Classifier
Sub Title (in English)
Keyword(1) support vector machinesoft cascadehardware architecture
1st Author's Name Eric Aliwarga
1st Author's Affiliation Osaka University(Osaka Univ.)
2nd Author's Name Jaehoon Yu
2nd Author's Affiliation Osaka University(Osaka Univ.)
3rd Author's Name Masahide Hatanaka
3rd Author's Affiliation Osaka University(Osaka Univ.)
4th Author's Name Takao Onoye
4th Author's Affiliation Osaka University(Osaka Univ.)
Date 2015-06-08
Paper # SIS2015-6
Volume (vol) vol.115
Number (no) SIS-75
Page pp.pp.29-34(SIS),
#Pages 6
Date of Issue 2015-06-01 (SIS)