| Presentation | 2015-04-17 Design and Implementation of FPGA-based Sorting Accelerator Ryohei Kobayashi, Kenji Kise, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Sorting is an extremely important computation kernel that has been tried to be accelerated in a lot of fields, such as database, image processing, data compression and so on. We propose an FPGA-based accelerator that executes sorting at high speed. FPGA-based accelerators can achieve higher computation performance than CPUs and GPUs, because designers can implement circuits that realize application-specific pipelined hardware and data supply system. Our proposed FPGA accelerator uses two approaches: “Sorting Network” and “Merge Sorter Tree”. In this paper, we detail design and implementation of the proposed sorting accelerator, and evaluate this performance. As a result, the sorting speed of the proposed hardware is up to 10.06x than Intel Core i7-4770 operating at 3.4GHz. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Accelerator / Sorting |
| Paper # | CPSY2015-5,DC2015-5 |
| Date of Issue | 2015-04-10 (CPSY, DC) |
| Conference Information | |
| Committee | DC / CPSY |
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| Conference Date | 2015/4/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Nobuyasu Kanekawa(Hitachi) / Tsutomu Yoshinaga(Univ. of Electro-Comm.) |
| Vice Chair | Michiko Inoue(NAIST) / Akira Asato(Fujitsu) / Yasuhiko Nakajima(NAIST) |
| Secretary | Michiko Inoue(RTRI) / Akira Asato(Osaka Univ.) / Yasuhiko Nakajima(Hiroshima Univ.) |
| Assistant | / Hiroaki Inoue(NEC) / Takeshi Ohkawa(Utsunomiya Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing / Technical Committee on Computer Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Implementation of FPGA-based Sorting Accelerator |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Accelerator |
| Keyword(3) | Sorting |
| 1st Author's Name | Ryohei Kobayashi |
| 1st Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 2nd Author's Name | Kenji Kise |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| Date | 2015-04-17 |
| Paper # | CPSY2015-5,DC2015-5 |
| Volume (vol) | vol.115 |
| Number (no) | CPSY-7,DC-8 |
| Page | pp.pp.25-30(CPSY), pp.25-30(DC), |
| #Pages | 6 |
| Date of Issue | 2015-04-10 (CPSY, DC) |