| Presentation | 2015-04-17 CGRA in Cache for Graph Applications Shohei Takeuchi, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, CGRA has been suggested high-speed and lower power consumption of graph processing. Generally, CGRA is connected via a bus to a different location from the general-purpose processor. So that, number of cache misses being increased by the pre-processing such as data transfer between general-purpose processor to CGRA, has become an obstacle to performance improvement. Therefore, in order to reduce data movement, we propose a structure of the CGRA in Cache which is included in the general-purpose processor's cache memory. This structure shares the L2 cache in general-purpose processor and local memory in CGRA, to reduce data movement. In this paper, we describe the structure and functions of the CGRA in Cache. Additionally, we estimated performance in the case where the overhead of data movement is reduced by half. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Graph Processing / CGRA / Accelerator / Cache memory |
| Paper # | CPSY2015-7,DC2015-7 |
| Date of Issue | 2015-04-10 (CPSY, DC) |
| Conference Information | |
| Committee | DC / CPSY |
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| Conference Date | 2015/4/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Nobuyasu Kanekawa(Hitachi) / Tsutomu Yoshinaga(Univ. of Electro-Comm.) |
| Vice Chair | Michiko Inoue(NAIST) / Akira Asato(Fujitsu) / Yasuhiko Nakajima(NAIST) |
| Secretary | Michiko Inoue(RTRI) / Akira Asato(Osaka Univ.) / Yasuhiko Nakajima(Hiroshima Univ.) |
| Assistant | / Hiroaki Inoue(NEC) / Takeshi Ohkawa(Utsunomiya Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing / Technical Committee on Computer Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | CGRA in Cache for Graph Applications |
| Sub Title (in English) | |
| Keyword(1) | Graph Processing |
| Keyword(2) | CGRA |
| Keyword(3) | Accelerator |
| Keyword(4) | Cache memory |
| 1st Author's Name | Shohei Takeuchi |
| 1st Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 2nd Author's Name | Thi Hong Tran |
| 2nd Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 3rd Author's Name | Shinya Takamaeda |
| 3rd Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 4th Author's Name | Yasuhiko Nakashima |
| 4th Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| Date | 2015-04-17 |
| Paper # | CPSY2015-7,DC2015-7 |
| Volume (vol) | vol.115 |
| Number (no) | CPSY-7,DC-8 |
| Page | pp.pp.37-41(CPSY), pp.37-41(DC), |
| #Pages | 5 |
| Date of Issue | 2015-04-10 (CPSY, DC) |