| Presentation | 2024-03-11 A power factor correction Circuit with supprressing the output voltage Haruki Kanto, Takamune Kabashima, Yoichi Ishizuka, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | AC-DC conversion circuits are used in many electrical devices and must convert AC voltage to stable DC voltage. They also need to comply with harmonic standards, which are strictly regulated worldwide due to environmental considerations. Normally, an AC-DC converter circuit consists of a two-stage power conversion circuit: a power factor correction (PFC) circuit that improves the power factor while converting AC voltage to DC voltage, and an isolated DC-DC converter that steps down that voltage to the voltage required by the load. In this circuit configuration, the voltage boost in the PFC circuit causes large losses in the transformer with a high step-down ratio. Therefore, this paper proposes a PFC circuit that can convert the voltage required by the load in a single stage and satisfies harmonic standards. Simulation results show that the power efficiency is up to 95% and the power factor is up to 0.997. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Power Factor Correction / Bridgeless PFC / Switched Capacitor Circuits |
| Paper # | EE2023-57 |
| Date of Issue | 2024-03-04 (EE) |
| Conference Information | |
| Committee | EE |
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| Conference Date | 2024/3/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Yoshiyasu Nakashima(NXTEC) |
| Vice Chair | Hiroo Sekiya(Chiba Univ.) / Hiroaki Kusawake(JAXA) |
| Secretary | Hiroo Sekiya(Aichi Inst. of Tech.) / Hiroaki Kusawake(Nagasaki Inst. of Applied Science) |
| Assistant | Yuu Yonezawa(Nagoya Univ.) / Yudai Furukawa(Nagasaki Inst. of Applied Science) / Kazufumi Yuasa(NTT Facilities) |
| Paper Information | |
| Registration To | Technical Committee on Energy Engineering in Electronics and Communications |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A power factor correction Circuit with supprressing the output voltage |
| Sub Title (in English) | |
| Keyword(1) | Power Factor Correction |
| Keyword(2) | Bridgeless PFC |
| Keyword(3) | Switched Capacitor Circuits |
| 1st Author's Name | Haruki Kanto |
| 1st Author's Affiliation | Nagasaki University(Nagasaki Univ.) |
| 2nd Author's Name | Takamune Kabashima |
| 2nd Author's Affiliation | Nagasaki University(Nagasaki Univ.) |
| 3rd Author's Name | Yoichi Ishizuka |
| 3rd Author's Affiliation | Nagasaki University(Nagasaki Univ.) |
| Date | 2024-03-11 |
| Paper # | EE2023-57 |
| Volume (vol) | vol.123 |
| Number (no) | EE-420 |
| Page | pp.pp.1-5(EE), |
| #Pages | 5 |
| Date of Issue | 2024-03-04 (EE) |