Presentation 2024-02-21
[Invited Talk] Development of Backside Buried Metal Layer Technology to Enhance Power Integrity of Three-Dimensional Integrated Circuits
Naoya Watanabe, Yuuki Araga, Haruo Shimamoto, Makoto Nagata, Katsuya Kikuchi,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English)
Keyword(in Japanese) (See Japanese page)
Keyword(in English)
Paper # SDM2023-83
Date of Issue 2024-02-14 (SDM)

Conference Information
Committee SDM
Conference Date 2024/2/21(1days)
Place (in Japanese) (See Japanese page)
Place (in English) Tokyo University-Hongo-Engineering Bldg.4
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Shunichiro Ohmi(Tokyo Inst. of Tech.)
Vice Chair Tatsuya Usami(Rapidus)
Secretary Tatsuya Usami(Tohoku Univ.)
Assistant Takuji Hosoi(Kwansei Gakuin Univ.) / Takuya Futase(Western Digital)

Paper Information
Registration To Technical Committee on Silicon Device and Materials
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) [Invited Talk] Development of Backside Buried Metal Layer Technology to Enhance Power Integrity of Three-Dimensional Integrated Circuits
Sub Title (in English)
Keyword(1)
1st Author's Name Naoya Watanabe
1st Author's Affiliation National Institute of Advanced Industrial Science and Technology(AIST)
2nd Author's Name Yuuki Araga
2nd Author's Affiliation National Institute of Advanced Industrial Science and Technology(AIST)
3rd Author's Name Haruo Shimamoto
3rd Author's Affiliation National Institute of Advanced Industrial Science and Technology(AIST)
4th Author's Name Makoto Nagata
4th Author's Affiliation Kobe University(Kobe Univ.)
5th Author's Name Katsuya Kikuchi
5th Author's Affiliation National Institute of Advanced Industrial Science and Technology(AIST)
Date 2024-02-21
Paper # SDM2023-83
Volume (vol) vol.123
Number (no) SDM-385
Page pp.pp.9-15(SDM),
#Pages 7
Date of Issue 2024-02-14 (SDM)