| Presentation | 2024-03-01 Hardware Design Based on Full Parameter Support and Parallelism Optimization for Key Encapsulation Mechanism FIPS203 Yuto Nakamura, Makoto Ikeda, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The emergence of quantum computers potentially threatens the security of traditional cryptographic techniques that depend on the difficulty of problems such as factorization and discrete logarithms. In recent years, there has been a movement towards standardizing post-quantum cryptography. In this study, we designed and optimized the parallelism of hardware for multiple parameter sets in key encapsulation mechanisms (KEMs) based on module lattices, in accordance with NIST's FIPS203. As a result of the optimization study, we logically synthesized hardware designed to match the parallelism to the number of columns in the matrices used. In this multi-parameter compatible hardware, we confirmed an area-time efficiency approximately 1.6 times greater than that of previous studies. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Post-Quantum Cryptography / Key encapsulation mechanism / CRYSTALS-Kyber / FIPS203 |
| Paper # | VLD2023-131,HWS2023-91,ICD2023-120 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |
| Conference Information | |
| Committee | VLD / HWS / ICD |
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| Conference Date | 2024/2/28(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Daisuke Suzuki(Mitsubishi Electric) / Makoto Ikeda(Univ. of Tokyo) |
| Vice Chair | Yuichi Sakurai(Hitachi) / Yuichi Hayashi(NAIST) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(Sony Semiconductor Solutions) |
| Secretary | Yuichi Sakurai(Socionext) / Yuichi Hayashi(Hirosaki Univ.) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(AIST) |
| Assistant | Takuma Nishimoto(Hitachi) / / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hardware Design Based on Full Parameter Support and Parallelism Optimization for Key Encapsulation Mechanism FIPS203 |
| Sub Title (in English) | |
| Keyword(1) | Post-Quantum Cryptography |
| Keyword(2) | Key encapsulation mechanism |
| Keyword(3) | CRYSTALS-Kyber |
| Keyword(4) | FIPS203 |
| 1st Author's Name | Yuto Nakamura |
| 1st Author's Affiliation | The University of Tokyo(UTokyo) |
| 2nd Author's Name | Makoto Ikeda |
| 2nd Author's Affiliation | The University of Tokyo(UTokyo) |
| Date | 2024-03-01 |
| Paper # | VLD2023-131,HWS2023-91,ICD2023-120 |
| Volume (vol) | vol.123 |
| Number (no) | VLD-390,HWS-391,ICD-392 |
| Page | pp.pp.167-172(VLD), pp.167-172(HWS), pp.167-172(ICD), |
| #Pages | 6 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |