| Presentation | 2024-03-02 A Study on formal verification of GF(2^m) arithmetic circuits including states Kazuho Sakoda, Yasuyoshi Uemura, Naofumi Homma, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes a formal verification method for arithmetic circuits based on computer algebra. Conventional methods usually target only combinational circuits and have difficulty in applying to sequential circuits including control states. In this paper, we discuss an extension to enable the formal verification of such arithmetic sequential circuits. We show the validity of the proposed method through some experiments. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | formal verification / computer algebra / cryptography / Galois field arithmetic circuits |
| Paper # | VLD2023-140,HWS2023-100,ICD2023-129 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |
| Conference Information | |
| Committee | VLD / HWS / ICD |
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| Conference Date | 2024/2/28(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Daisuke Suzuki(Mitsubishi Electric) / Makoto Ikeda(Univ. of Tokyo) |
| Vice Chair | Yuichi Sakurai(Hitachi) / Yuichi Hayashi(NAIST) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(Sony Semiconductor Solutions) |
| Secretary | Yuichi Sakurai(Socionext) / Yuichi Hayashi(Hirosaki Univ.) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(AIST) |
| Assistant | Takuma Nishimoto(Hitachi) / / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study on formal verification of GF(2^m) arithmetic circuits including states |
| Sub Title (in English) | |
| Keyword(1) | formal verification |
| Keyword(2) | computer algebra |
| Keyword(3) | cryptography |
| Keyword(4) | Galois field arithmetic circuits |
| 1st Author's Name | Kazuho Sakoda |
| 1st Author's Affiliation | SCU Co., Ltd./Kobe University(SCU/Kobe Univ.) |
| 2nd Author's Name | Yasuyoshi Uemura |
| 2nd Author's Affiliation | SCU Co., Ltd.(SCU) |
| 3rd Author's Name | Naofumi Homma |
| 3rd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| Date | 2024-03-02 |
| Paper # | VLD2023-140,HWS2023-100,ICD2023-129 |
| Volume (vol) | vol.123 |
| Number (no) | VLD-390,HWS-391,ICD-392 |
| Page | pp.pp.215-220(VLD), pp.215-220(HWS), pp.215-220(ICD), |
| #Pages | 6 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |