| Presentation | 2024-03-02 eFPGA-based IP Protection of Embedded Processor Design Tomosuke Ichioka, Tanvir Ahmed, Yuko Hara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As manufacturing costs continue to grow, IC manufacturers are increasingly outsourcing IC manufacturing to third-party foundries in order to reduce the cost of manufacturing equipment. As a result, problems such as IP theft and unauthorized manufacturing are becoming more serious. This study focuses on IP protection by circuit replacement using eFPGA as a solution to this problem. Assuming a case where IP protection is applied to the circuit design of a processor, we focus on the versatility of the processor and evaluate the effects (i.e., IP protection and circuit overhead) of circuit replacement by eFPGA from the application perspective. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Embedded FPGA (eFPGA) / IP Protection / SAT Attack |
| Paper # | VLD2023-139,HWS2023-99,ICD2023-128 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |
| Conference Information | |
| Committee | VLD / HWS / ICD |
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| Conference Date | 2024/2/28(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Daisuke Suzuki(Mitsubishi Electric) / Makoto Ikeda(Univ. of Tokyo) |
| Vice Chair | Yuichi Sakurai(Hitachi) / Yuichi Hayashi(NAIST) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(Sony Semiconductor Solutions) |
| Secretary | Yuichi Sakurai(Socionext) / Yuichi Hayashi(Hirosaki Univ.) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(AIST) |
| Assistant | Takuma Nishimoto(Hitachi) / / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | eFPGA-based IP Protection of Embedded Processor Design |
| Sub Title (in English) | |
| Keyword(1) | Embedded FPGA (eFPGA) |
| Keyword(2) | IP Protection |
| Keyword(3) | SAT Attack |
| 1st Author's Name | Tomosuke Ichioka |
| 1st Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 2nd Author's Name | Tanvir Ahmed |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 3rd Author's Name | Yuko Hara |
| 3rd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| Date | 2024-03-02 |
| Paper # | VLD2023-139,HWS2023-99,ICD2023-128 |
| Volume (vol) | vol.123 |
| Number (no) | VLD-390,HWS-391,ICD-392 |
| Page | pp.pp.209-214(VLD), pp.209-214(HWS), pp.209-214(ICD), |
| #Pages | 6 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |