| Presentation | 2024-03-02 Design of General Hardware for Optimal Strategy in Isogeny-Based Post-Quantum Cryptography Kosei Nakamura, Makoto Ikeda, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The computation in isogeny-based post-quantum cryptography primarily consists of two operations: scalar multiplication on elliptic curves and mapping points from one elliptic curve to another. Since these two computations are commutative, countless computational paths (strategy) can be considered, and the time and space complexity varies depending on the computational path chosen. By creating general-purpose hardware capable of executing all computational paths, and using thishardware to compare factors such as latency and memory requirements for each path, an investigation was conducted to identifythe optimal computational path for hardware acceleration. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | PQC / Isogeny / SIKE / SIDH / strategy / hardware accelerator |
| Paper # | VLD2023-137,HWS2023-97,ICD2023-126 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |
| Conference Information | |
| Committee | VLD / HWS / ICD |
|---|---|
| Conference Date | 2024/2/28(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Daisuke Suzuki(Mitsubishi Electric) / Makoto Ikeda(Univ. of Tokyo) |
| Vice Chair | Yuichi Sakurai(Hitachi) / Yuichi Hayashi(NAIST) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(Sony Semiconductor Solutions) |
| Secretary | Yuichi Sakurai(Socionext) / Yuichi Hayashi(Hirosaki Univ.) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(AIST) |
| Assistant | Takuma Nishimoto(Hitachi) / / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of General Hardware for Optimal Strategy in Isogeny-Based Post-Quantum Cryptography |
| Sub Title (in English) | |
| Keyword(1) | PQC |
| Keyword(2) | Isogeny |
| Keyword(3) | SIKE |
| Keyword(4) | SIDH |
| Keyword(5) | strategy |
| Keyword(6) | hardware accelerator |
| 1st Author's Name | Kosei Nakamura |
| 1st Author's Affiliation | The University of Tokyo(UT) |
| 2nd Author's Name | Makoto Ikeda |
| 2nd Author's Affiliation | The University of Tokyo(UT) |
| Date | 2024-03-02 |
| Paper # | VLD2023-137,HWS2023-97,ICD2023-126 |
| Volume (vol) | vol.123 |
| Number (no) | VLD-390,HWS-391,ICD-392 |
| Page | pp.pp.198-203(VLD), pp.198-203(HWS), pp.198-203(ICD), |
| #Pages | 6 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |