| Presentation | 2024-03-01 Security Evaluation of Fault Analysis for SuperSonic Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | SuperSonic, a low-latency lightweight block cipher, is suitable for securing edge devices with high real-time performance. In order to deploy SuperSonic in real systems, it is very important to evaluate its security against various threats such as side-channel attacks. Typical side-channel attacks include power analysis focusing on power consumption and fault analysis focusing on arithmetic errors. Although the tamper resistance of SuperSonic has been evaluated for power analysis, the fault analysis has not been evaluated. Therefore, this study proposes a cryptographic algorithm-oriented fault analysis method to evaluate the security of SuperSonic. This study evaluates the arithmetic error rate of the proposed fault model by simulating fault injection. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | hardware security / fault analysis / lightweight block cipher / SuperSonic |
| Paper # | VLD2023-126,HWS2023-86,ICD2023-115 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |
| Conference Information | |
| Committee | VLD / HWS / ICD |
|---|---|
| Conference Date | 2024/2/28(4days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Daisuke Suzuki(Mitsubishi Electric) / Makoto Ikeda(Univ. of Tokyo) |
| Vice Chair | Yuichi Sakurai(Hitachi) / Yuichi Hayashi(NAIST) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(Sony Semiconductor Solutions) |
| Secretary | Yuichi Sakurai(Socionext) / Yuichi Hayashi(Hirosaki Univ.) / Toru Akishita(Sony Semiconductor Solutions) / Hayato Wakabayashi(AIST) |
| Assistant | Takuma Nishimoto(Hitachi) / / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Hardware Security / Technical Committee on Integrated Circuits and Devices |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Security Evaluation of Fault Analysis for SuperSonic |
| Sub Title (in English) | |
| Keyword(1) | hardware security |
| Keyword(2) | fault analysis |
| Keyword(3) | lightweight block cipher |
| Keyword(4) | SuperSonic |
| 1st Author's Name | Shu Takemoto |
| 1st Author's Affiliation | Meijo University(Meijo Univ.) |
| 2nd Author's Name | Yusuke Nozaki |
| 2nd Author's Affiliation | Meijo University(Meijo Univ.) |
| 3rd Author's Name | Masaya Yoshikawa |
| 3rd Author's Affiliation | Meijo University(Meijo Univ.) |
| Date | 2024-03-01 |
| Paper # | VLD2023-126,HWS2023-86,ICD2023-115 |
| Volume (vol) | vol.123 |
| Number (no) | VLD-390,HWS-391,ICD-392 |
| Page | pp.pp.141-144(VLD), pp.141-144(HWS), pp.141-144(ICD), |
| #Pages | 4 |
| Date of Issue | 2024-02-21 (VLD, HWS, ICD) |