| Presentation | 2023-12-07 Data Path Parallelization to Improve Performance of High-level Synthesized Sprite Drawing Hardware Yuka Otani, Akira Yamawaki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A mobile terminal architecture which can dynamically reconfigure the optimal hardware for each application can achieve higher performance and lower power consumption compared with a conventional one. We are developing a software game library so that the high-level synthesis, HLS, can automatically generate an efficient hardware module in such mobile terminals. The HLS library must be built with deep consideration of hardware organization. Otherwise, the HLS converts software into a large and slow hardware module. This paper focuses on the drawing of 2D sprite characters. Character movement is achieved by repeatedly compositing the background image and sprite image during drawing. The data paths are parallelized on the sprite drawing process so that the HLS can produce better hardware. The experiments confirm the effectiveness of the proposed method on the actual machine and simulation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High-Level Synthesis (HLS) / Sprite / Drawing / Game library / Parallel / FPGA / Low-power / High-performance |
| Paper # | SIS2023-24 |
| Date of Issue | 2023-11-30 (SIS) |
| Conference Information | |
| Committee | SIS |
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| Conference Date | 2023/12/7(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Sakurayama Campus, Nagoya City University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Smart Personal Sysytems, etc. |
| Chair | Tomoaki Kimura(Kanagawa Inst. of Tech.) |
| Vice Chair | Naoto Sasaoka(Tottori Univ.) / Hakaru Tamukoh(Kyushu Inst. of Tech.) |
| Secretary | Naoto Sasaoka(Kanagawa Inst. of Tech.) / Hakaru Tamukoh(Kansai Univ.) |
| Assistant | Yuichiro Tanaka(kyushu Inst. of Tech.) / Yosuke Sugiura(Saitama Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Smart Info-Media Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Data Path Parallelization to Improve Performance of High-level Synthesized Sprite Drawing Hardware |
| Sub Title (in English) | |
| Keyword(1) | High-Level Synthesis (HLS) |
| Keyword(2) | Sprite |
| Keyword(3) | Drawing |
| Keyword(4) | Game library |
| Keyword(5) | Parallel |
| Keyword(6) | FPGA |
| Keyword(7) | Low-power |
| Keyword(8) | High-performance |
| 1st Author's Name | Yuka Otani |
| 1st Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 2nd Author's Name | Akira Yamawaki |
| 2nd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| Date | 2023-12-07 |
| Paper # | SIS2023-24 |
| Volume (vol) | vol.123 |
| Number (no) | SIS-296 |
| Page | pp.pp.1-6(SIS), |
| #Pages | 6 |
| Date of Issue | 2023-11-30 (SIS) |