| Presentation | 2023-11-15 Error Correction Decoder of the Surface Code designed in a 22-nm Bulk Process for Fault Torelant Quantum Computers Ren Aoyama, Junichiro Kadomoto, Kazutoshi Kobayashi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Error correction is mandatory to realize a quantum computer that can perform practical calculations. Surface codes is one of typical error correction methods because of their high error correction capability. In this study, we designed an error decoder, which is a part of the error correction function, using Verilog HDL. The greedy algorithm is used in the design. The designed HDL was synthesized in a 22-nm bulk process to evaluate performance, power and area. Its area and power consumption are also evaluated by changing the number of nodes that can be stored in the decoder. As a result, it is confirmed that the circuit can operate up to 1 GHz with 40 entries. The area and power consumption were $mathrm{5.85mu m^2}$ and $mathrm{4.28mW}$, respectively. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Surface code / Quantum computer / Decoder / Error correction / Greedy algorithm |
| Paper # | VLD2023-38,ICD2023-46,DC2023-45,RECONF2023-41 |
| Date of Issue | 2023-11-08 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2023/11/15(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Civic Auditorium Sears Home Yume Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2023 -New Field of VLSI Design- |
| Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Tatsuhiro Tsuchiya(Osaka Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Makoto Ikeda(Univ. of Tokyo) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Yuichi Sakurai(Hitachi) / Toshinori Hosokawa(Nihon Univ.) / Yasushi Inoguchi(JAIST) / Tomonori Izumi(Ritsumeikan Univ.) / Hayato Wakabayashi(Sony Semiconductor Solutions) |
| Secretary | Yuichi Sakurai(Socionext) / Toshinori Hosokawa(Hirosaki Univ.) / Yasushi Inoguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Hayato Wakabayashi(NEC) / (Toyohashi Univ. of Tech.) |
| Assistant | Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Kumamoto Univ.) / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Kumamoto University) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Error Correction Decoder of the Surface Code designed in a 22-nm Bulk Process for Fault Torelant Quantum Computers |
| Sub Title (in English) | |
| Keyword(1) | Surface code |
| Keyword(2) | Quantum computer |
| Keyword(3) | Decoder |
| Keyword(4) | Error correction |
| Keyword(5) | Greedy algorithm |
| 1st Author's Name | Ren Aoyama |
| 1st Author's Affiliation | Kyoto Institute of Technology(KIT) |
| 2nd Author's Name | Junichiro Kadomoto |
| 2nd Author's Affiliation | The University of Tokyo(UTokyo) |
| 3rd Author's Name | Kazutoshi Kobayashi |
| 3rd Author's Affiliation | Kyoto Institute of Technology(KIT) |
| Date | 2023-11-15 |
| Paper # | VLD2023-38,ICD2023-46,DC2023-45,RECONF2023-41 |
| Volume (vol) | vol.123 |
| Number (no) | VLD-258,ICD-259,DC-260,RECONF-261 |
| Page | pp.pp.49-53(VLD), pp.49-53(ICD), pp.49-53(DC), pp.49-53(RECONF), |
| #Pages | 5 |
| Date of Issue | 2023-11-08 (VLD, ICD, DC, RECONF) |