| Presentation | 2023-11-17 同期式回路設計支援環境におけるMuller's C-elementの実装に関する一考察 Masashi Imai, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Muller’s C-element is a basic component often used to rendezvous signals in asynchronous circuit designs. A lot of implementation methods have been proposed and well studied. However, several structures may not be selectable depending on the selected manufacturing process and EDA tools. In this paper, we discuss how to design Muller’s C-element according to the constraints specified using only standard cells in the selected cell library. The transistor level circuit structures are also discussed under the assumption which can design original cells. A new structure of a C-element using a D-latch will be also proposed. It is confirmed that the proposed structure has approximately twice the number of transistors compared to the traditional structures and the delay overhead is about 1.2 times larger than those. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Asynchronous circuit / Muller's C-element / D-Latch / Latch based structure |
| Paper # | VLD2023-79,ICD2023-87,DC2023-86,RECONF2023-82 |
| Date of Issue | 2023-11-08 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2023/11/15(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Civic Auditorium Sears Home Yume Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2023 -New Field of VLSI Design- |
| Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Tatsuhiro Tsuchiya(Osaka Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Makoto Ikeda(Univ. of Tokyo) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Yuichi Sakurai(Hitachi) / Toshinori Hosokawa(Nihon Univ.) / Yasushi Inoguchi(JAIST) / Tomonori Izumi(Ritsumeikan Univ.) / Hayato Wakabayashi(Sony Semiconductor Solutions) |
| Secretary | Yuichi Sakurai(Socionext) / Toshinori Hosokawa(Hirosaki Univ.) / Yasushi Inoguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Hayato Wakabayashi(NEC) / (Toyohashi Univ. of Tech.) |
| Assistant | Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Kumamoto Univ.) / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Kumamoto University) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | |
| Sub Title (in English) | |
| Keyword(1) | Asynchronous circuit |
| Keyword(2) | Muller's C-element |
| Keyword(3) | D-Latch |
| Keyword(4) | Latch based structure |
| 1st Author's Name | Masashi Imai |
| 1st Author's Affiliation | Hirosaki University(Hirosaki Univ.) |
| Date | 2023-11-17 |
| Paper # | VLD2023-79,ICD2023-87,DC2023-86,RECONF2023-82 |
| Volume (vol) | vol.123 |
| Number (no) | VLD-258,ICD-259,DC-260,RECONF-261 |
| Page | pp.pp.255-260(VLD), pp.255-260(ICD), pp.255-260(DC), pp.255-260(RECONF), |
| #Pages | 6 |
| Date of Issue | 2023-11-08 (VLD, ICD, DC, RECONF) |