| Presentation | 2023-11-15 多重量子化オプティマイザを用いたエッジAIオンライン学習アーキテクチャの提案 Itsuki Akeno, Hiro Yamazaki, Tetsuya Asai, Kota Ando, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose a processor architecture for neural network (NN) training in edge and prototype it on an FPGA (Field--Programmable Gate Array). Currently, neural networks are widely employed in arti?cial intelligence (AI), and there is a pressing need for the development of dedicated hardware for edge side AI training. To address this demand, the Holmes optimizer has been proposed and proved to have capability of faster convergence with a smaller memory footprint compared toother optimizers. Therefore, this paper presents a hardware architecture that incorporates Holmes and leverages parallelization and pipelining techniques to achieve signi?can't throughput improvements. Furthermore, based on this architecture, we evaluated the hardware resource consumption of the proposed architecture by implementing it on an FPGA. This research focuseson proposing a hardware architecture suitable for neural network learning and its FPGA implementation. It contributes to theadvancement of hardware for neural network-based AI learning, which is of paramount importance given the widespread usageof neural networks in AI applications. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Neural Network / Edge Computing / Architecture / FPGA / Optimizer |
| Paper # | VLD2023-41,ICD2023-49,DC2023-48,RECONF2023-44 |
| Date of Issue | 2023-11-08 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2023/11/15(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Civic Auditorium Sears Home Yume Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2023 -New Field of VLSI Design- |
| Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Tatsuhiro Tsuchiya(Osaka Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Makoto Ikeda(Univ. of Tokyo) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Yuichi Sakurai(Hitachi) / Toshinori Hosokawa(Nihon Univ.) / Yasushi Inoguchi(JAIST) / Tomonori Izumi(Ritsumeikan Univ.) / Hayato Wakabayashi(Sony Semiconductor Solutions) |
| Secretary | Yuichi Sakurai(Socionext) / Toshinori Hosokawa(Hirosaki Univ.) / Yasushi Inoguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Hayato Wakabayashi(NEC) / (Toyohashi Univ. of Tech.) |
| Assistant | Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Kumamoto Univ.) / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Kumamoto University) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | |
| Sub Title (in English) | |
| Keyword(1) | Neural Network |
| Keyword(2) | Edge Computing |
| Keyword(3) | Architecture |
| Keyword(4) | FPGA |
| Keyword(5) | Optimizer |
| 1st Author's Name | Itsuki Akeno |
| 1st Author's Affiliation | Hokkaido University(Hokkaido Univ) |
| 2nd Author's Name | Hiro Yamazaki |
| 2nd Author's Affiliation | Hokkaido University(Hokkaido Univ) |
| 3rd Author's Name | Tetsuya Asai |
| 3rd Author's Affiliation | Hokkaido University(Hokkaido Univ) |
| 4th Author's Name | Kota Ando |
| 4th Author's Affiliation | Hokkaido University(Hokkaido Univ) |
| Date | 2023-11-15 |
| Paper # | VLD2023-41,ICD2023-49,DC2023-48,RECONF2023-44 |
| Volume (vol) | vol.123 |
| Number (no) | VLD-258,ICD-259,DC-260,RECONF-261 |
| Page | pp.pp.64-69(VLD), pp.64-69(ICD), pp.64-69(DC), pp.64-69(RECONF), |
| #Pages | 6 |
| Date of Issue | 2023-11-08 (VLD, ICD, DC, RECONF) |