| Presentation | 2023-11-16 Attack Verification and Evaluation of Incremental Fault Analysis against AES Encryption Processing Device Miran Tamagawa, Yuichi Futa, Takehiko Mieno, Hiroyuki Okazaki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years，there has been a growing concern about the impact of fault analysis attack，which use hardware failures against cryptographic implementation devices to promote information leak．Trevor E．Pogue et al． proposed Incremental Fault Analysis and used incremental fault information to extract AES secret keys．In the study by Kato et al.，Incremental Fault Analysis is evaluated by creating a probabilistic model，and it is found that the attack accuracy of Incremental Fault Analysis may be improved even when the fault tolerance is weak．Problems of the two previous studies are the lack of evaluation of Incremental Fault Analysis, and no practical experiment environments．In this report，we construct a new evaluation environment for fault analysis attack using DDS and a microcomputer board．Then，we evaluate whether or not multiple failures，which are essential in Incremental Fault Analysis，occur，and analyze the output encrypted information． |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Hardware Security / Side Channel Attack / Fault Analysis Attack / Incremental Fault Analysis |
| Paper # | ICSS2023-56 |
| Date of Issue | 2023-11-09 (ICSS) |
| Conference Information | |
| Committee | ICSS |
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| Conference Date | 2023/11/16(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | IT Business Plaza Musashi and Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Security, etc. |
| Chair | Daisuke Inoue(NICT) |
| Vice Chair | Akira Yamada(Kobe Univ.) / Toshihiro Yamauchi(Okayama Univ.) |
| Secretary | Akira Yamada(Mitsubishi Electric) / Toshihiro Yamauchi(Univ. of Electro-Comm.) |
| Assistant | Yo Kanemoto(NTT) / Masaya Sato(Okayama Prefectural Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Information and Communication System Security |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Attack Verification and Evaluation of Incremental Fault Analysis against AES Encryption Processing Device |
| Sub Title (in English) | |
| Keyword(1) | Hardware Security |
| Keyword(2) | Side Channel Attack |
| Keyword(3) | Fault Analysis Attack |
| Keyword(4) | Incremental Fault Analysis |
| 1st Author's Name | Miran Tamagawa |
| 1st Author's Affiliation | Tokyo University of Technology Graduate School(TUT) |
| 2nd Author's Name | Yuichi Futa |
| 2nd Author's Affiliation | Tokyo University of Technology(TUT) |
| 3rd Author's Name | Takehiko Mieno |
| 3rd Author's Affiliation | EPSON AVASYS Corporation(AVASYS) |
| 4th Author's Name | Hiroyuki Okazaki |
| 4th Author's Affiliation | Shinshu University(Shinshu University) |
| Date | 2023-11-16 |
| Paper # | ICSS2023-56 |
| Volume (vol) | vol.123 |
| Number (no) | ICSS-269 |
| Page | pp.pp.35-41(ICSS), |
| #Pages | 7 |
| Date of Issue | 2023-11-09 (ICSS) |