Presentation 2023-11-16
Analysis and Improvement of the Parallel Implementation of Linear FSMs for Reducing the Latency in Stochastic Computing
Kota Okahara, Hideyuki Ichihara, Tomoo Inoue,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) In stochastic computing, which is a computational method with probabilities, various one-input functions, such as absolute value function, hyperbolic tangent function and so on, can be approximately calculated with linear finite state machines (linear FSMs). To reduce the latency of stochastic computing with linear FSMs, a parallel implementation method, in which several linear FSMs are implemented in parallel and the initial states of the linear FSMs are controlled so as to increase the calculation accuracy, has been proposed. In this study, we clarify the detailed design of the parallel implementation of linear FSMs and unveil the effect of the number of the cycles required to estimate the input values to the calculation accuracy and the circuit area size. Moreover, we propose a novel implementation method with multi-input linear FSMs in order to achieve more accurate calculation. Experimental analysis shows that the proposed parallel implementation method can attain the high calculation accuracy, which is equivalent to that single linear FSMs can achieve, with a few estimation cycles and small hardware cost.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Approximate computing / Acceleration / Calculation error / Hardware cost / Input value estimation / Multi-input linear FSMs
Paper # VLD2023-50,ICD2023-58,DC2023-57,RECONF2023-53
Date of Issue 2023-11-08 (VLD, ICD, DC, RECONF)

Conference Information
Committee VLD / DC / RECONF / ICD / IPSJ-SLDM
Conference Date 2023/11/15(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Civic Auditorium Sears Home Yume Hall
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2023 -New Field of VLSI Design-
Chair Shigetoshi Nakatake(Univ. of Kitakyushu) / Tatsuhiro Tsuchiya(Osaka Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Makoto Ikeda(Univ. of Tokyo) / Hiroyuki Ochi(Ritsumeikan Univ.)
Vice Chair Yuichi Sakurai(Hitachi) / Toshinori Hosokawa(Nihon Univ.) / Yasushi Inoguchi(JAIST) / Tomonori Izumi(Ritsumeikan Univ.) / Hayato Wakabayashi(Sony Semiconductor Solutions)
Secretary Yuichi Sakurai(Socionext) / Toshinori Hosokawa(Hirosaki Univ.) / Yasushi Inoguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Hayato Wakabayashi(NEC) / (Toyohashi Univ. of Tech.)
Assistant Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Kumamoto Univ.) / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Kumamoto University)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Analysis and Improvement of the Parallel Implementation of Linear FSMs for Reducing the Latency in Stochastic Computing
Sub Title (in English)
Keyword(1) Approximate computing
Keyword(2) Acceleration
Keyword(3) Calculation error
Keyword(4) Hardware cost
Keyword(5) Input value estimation
Keyword(6) Multi-input linear FSMs
1st Author's Name Kota Okahara
1st Author's Affiliation Hiroshima City University(Hiroshima City Univ.)
2nd Author's Name Hideyuki Ichihara
2nd Author's Affiliation Hiroshima City University(Hiroshima City Univ.)
3rd Author's Name Tomoo Inoue
3rd Author's Affiliation Hiroshima City University(Hiroshima City Univ.)
Date 2023-11-16
Paper # VLD2023-50,ICD2023-58,DC2023-57,RECONF2023-53
Volume (vol) vol.123
Number (no) VLD-258,ICD-259,DC-260,RECONF-261
Page pp.pp.106-111(VLD), pp.106-111(ICD), pp.106-111(DC), pp.106-111(RECONF),
#Pages 6
Date of Issue 2023-11-08 (VLD, ICD, DC, RECONF)