Presentation | 2023-11-16 Tamper Resistance Evaluation on FPGA for Low-Latency Cipher Sonic Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Industry 5.0 promotes smart factories for system optimization by utilizing IoT and AI in the industrial field. The smart factory requires high real-time performance to improve the efficiency of production lines and security for confidential data such as corporate know-how and customer information. Therefore, low-latency lightweight block ciphers, which are one of the cryptographic techniques that can both ensure security and suppress the overhead of computational latency, are important elemental technologies for the construction of secure smart factories. Also, it is very important to evaluate the tamper-resistance of cryptographic on real devices due to the reported threat of deep learning side-channel attacks, which learn physical information during hardware implementation and analyze the secret key using deep learning. Therefore, this study evaluates the tamper resistance of Sonic, a state-of-the-art low-latency lightweight block cipher implemented unrolled on FPGAs, against deep learning side-channel attacks. The analysis method uses a Hamming-weighted power model focusing on the AND operations included in Sonic. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Hardware Security / Lightweight Block Cipher / Side-Channel Attack / Sonic |
Paper # | VLD2023-49,ICD2023-57,DC2023-56,RECONF2023-52 |
Date of Issue | 2023-11-08 (VLD, ICD, DC, RECONF) |
Conference Information | |
Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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Conference Date | 2023/11/15(3days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | Civic Auditorium Sears Home Yume Hall |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | Design Gaia 2023 -New Field of VLSI Design- |
Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Tatsuhiro Tsuchiya(Osaka Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Makoto Ikeda(Univ. of Tokyo) / Hiroyuki Ochi(Ritsumeikan Univ.) |
Vice Chair | Yuichi Sakurai(Hitachi) / Toshinori Hosokawa(Nihon Univ.) / Yasushi Inoguchi(JAIST) / Tomonori Izumi(Ritsumeikan Univ.) / Hayato Wakabayashi(Sony Semiconductor Solutions) |
Secretary | Yuichi Sakurai(Socionext) / Toshinori Hosokawa(Hirosaki Univ.) / Yasushi Inoguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Hayato Wakabayashi(NEC) / (Toyohashi Univ. of Tech.) |
Assistant | Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Kumamoto Univ.) / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Kumamoto University) |
Paper Information | |
Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Tamper Resistance Evaluation on FPGA for Low-Latency Cipher Sonic |
Sub Title (in English) | |
Keyword(1) | Hardware Security |
Keyword(2) | Lightweight Block Cipher |
Keyword(3) | Side-Channel Attack |
Keyword(4) | Sonic |
1st Author's Name | Shu Takemoto |
1st Author's Affiliation | Meijo University(Meijo Univ.) |
2nd Author's Name | Yusuke Nozaki |
2nd Author's Affiliation | Meijo University(Meijo Univ.) |
3rd Author's Name | Masaya Yoshikawa |
3rd Author's Affiliation | Meijo University(Meijo Univ.) |
Date | 2023-11-16 |
Paper # | VLD2023-49,ICD2023-57,DC2023-56,RECONF2023-52 |
Volume (vol) | vol.123 |
Number (no) | VLD-258,ICD-259,DC-260,RECONF-261 |
Page | pp.pp.101-105(VLD), pp.101-105(ICD), pp.101-105(DC), pp.101-105(RECONF), |
#Pages | 5 |
Date of Issue | 2023-11-08 (VLD, ICD, DC, RECONF) |