| Presentation | 2023-11-15 A 183.4 nJ/inference 152.8 ?W Single-Chip Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application Rei Sumikawa, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A 183.4-nJ/inference single-chip wired-logic DNN processor that is capable of recognizing all 35 commands defined in the industrial standard voice recognition data set (Google Speech Command Dataset) is developed. The algorithm-circuit co-optimized processor recognizes 3.5 times more commands with 1.6 times higher energy efficiency than the state-of-the-art analog processor while keeping design cost low. By implementing all the processing circuits and wiring required for the 16-layer DNN onto a single chip, the need to store weight coefficients and intermediate data in DRAM/SRAM is eliminated. Owing to the proposed architecture, a low power consumption of 152.8 ?W is achieved, which is low enough for always-on applications on battery-powered IoT devices. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DNN / AI processor / Wired-logic / Algorithm-circuit co-optimization |
| Paper # | VLD2023-39,ICD2023-47,DC2023-46,RECONF2023-42 |
| Date of Issue | 2023-11-08 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2023/11/15(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Civic Auditorium Sears Home Yume Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2023 -New Field of VLSI Design- |
| Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Tatsuhiro Tsuchiya(Osaka Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Makoto Ikeda(Univ. of Tokyo) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Yuichi Sakurai(Hitachi) / Toshinori Hosokawa(Nihon Univ.) / Yasushi Inoguchi(JAIST) / Tomonori Izumi(Ritsumeikan Univ.) / Hayato Wakabayashi(Sony Semiconductor Solutions) |
| Secretary | Yuichi Sakurai(Socionext) / Toshinori Hosokawa(Hirosaki Univ.) / Yasushi Inoguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Hayato Wakabayashi(NEC) / (Toyohashi Univ. of Tech.) |
| Assistant | Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Kumamoto Univ.) / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Kumamoto University) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 183.4 nJ/inference 152.8 ?W Single-Chip Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application |
| Sub Title (in English) | |
| Keyword(1) | DNN |
| Keyword(2) | AI processor |
| Keyword(3) | Wired-logic |
| Keyword(4) | Algorithm-circuit co-optimization |
| 1st Author's Name | Rei Sumikawa |
| 1st Author's Affiliation | The University of Tokyo(UTokyo) |
| 2nd Author's Name | Atsutake Kosuge |
| 2nd Author's Affiliation | The University of Tokyo(UTokyo) |
| 3rd Author's Name | Mototsugu Hamada |
| 3rd Author's Affiliation | The University of Tokyo(UTokyo) |
| 4th Author's Name | Tadahiro Kuroda |
| 4th Author's Affiliation | The University of Tokyo(UTokyo) |
| Date | 2023-11-15 |
| Paper # | VLD2023-39,ICD2023-47,DC2023-46,RECONF2023-42 |
| Volume (vol) | vol.123 |
| Number (no) | VLD-258,ICD-259,DC-260,RECONF-261 |
| Page | pp.pp.54-59(VLD), pp.54-59(ICD), pp.54-59(DC), pp.54-59(RECONF), |
| #Pages | 6 |
| Date of Issue | 2023-11-08 (VLD, ICD, DC, RECONF) |