| Presentation | 2023-11-16 Proposal of MTJ-based non-volatile flip-flops using reference resistance and Two-step Store Control Kousei Kaizu, Kimiyoshi Usami, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Non-Volatile Flip Flops (NVFF) using Magnetic Tunnel Junction (MTJ) enable non-volatile power gating and reduce leakage power. However, MTJ has the problem of high write energy. Conventional NVFFs write to two MTJs per NVFF because they read using the difference between the high and low resistance of the MTJs. However, it is not necessary to write to two MTJs, if they can be accurately read using one MTJ and a reference resistor whose resistance value is fixed between high and low resistance. In this study, we propose an NVFF circuit that has a reference resistor and writes to only one MTJ to reduce energy. We conducted circuit design and layout in the 65nm process technology. Simulation results demonstrated that the write energy was reduced by 51~58% while suppressing the area overhead to 6%. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MTJ / Non-volatile flip-flops / Power Gating |
| Paper # | VLD2023-45,ICD2023-53,DC2023-52,RECONF2023-48 |
| Date of Issue | 2023-11-08 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2023/11/15(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Civic Auditorium Sears Home Yume Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2023 -New Field of VLSI Design- |
| Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Tatsuhiro Tsuchiya(Osaka Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Makoto Ikeda(Univ. of Tokyo) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Yuichi Sakurai(Hitachi) / Toshinori Hosokawa(Nihon Univ.) / Yasushi Inoguchi(JAIST) / Tomonori Izumi(Ritsumeikan Univ.) / Hayato Wakabayashi(Sony Semiconductor Solutions) |
| Secretary | Yuichi Sakurai(Socionext) / Toshinori Hosokawa(Hirosaki Univ.) / Yasushi Inoguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Hayato Wakabayashi(NEC) / (Toyohashi Univ. of Tech.) |
| Assistant | Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Kumamoto Univ.) / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Kumamoto University) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Proposal of MTJ-based non-volatile flip-flops using reference resistance and Two-step Store Control |
| Sub Title (in English) | |
| Keyword(1) | MTJ |
| Keyword(2) | Non-volatile flip-flops |
| Keyword(3) | Power Gating |
| 1st Author's Name | Kousei Kaizu |
| 1st Author's Affiliation | Shibaura Institute of Technology(SIT) |
| 2nd Author's Name | Kimiyoshi Usami |
| 2nd Author's Affiliation | Shibaura Institute of Technology(SIT) |
| Date | 2023-11-16 |
| Paper # | VLD2023-45,ICD2023-53,DC2023-52,RECONF2023-48 |
| Volume (vol) | vol.123 |
| Number (no) | VLD-258,ICD-259,DC-260,RECONF-261 |
| Page | pp.pp.88-93(VLD), pp.88-93(ICD), pp.88-93(DC), pp.88-93(RECONF), |
| #Pages | 6 |
| Date of Issue | 2023-11-08 (VLD, ICD, DC, RECONF) |