| Presentation | 2023-11-16 On Reducing Area Overhead of BIST for Approximate Multiplier Considering Truncated Bits Daichi Akamatsu, Shougo Tokai, Hiroyuki Yotsuyanagi, Masaki Hashizume, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, approximate computing has attracted attention as a method to reduce power and area for error-tolerant applications with an acceptable loss of accuracy. As an approximation method for multipliers, truncation of lower bits based on the number of significant digits of the multiplier and the multiplicand has been proposed. In this study, we propose a method to reduce the size of the test pattern generation circuit (PRPG) used in built-in self-test (BIST) by considering the bits to be truncated as a testability design for approximate multipliers. Since our method provides test patterns evenly for each truncation condition using a smaller PRPG, we confirmed that the proposed method can reduce the area overhead of PRPG by up to approximately 42% and also achieve higher test coverage. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | BIST / approximate computing / multiplier / test cost reduction |
| Paper # | VLD2023-60,ICD2023-68,DC2023-67,RECONF2023-63 |
| Date of Issue | 2023-11-08 (VLD, ICD, DC, RECONF) |
| Conference Information | |
| Committee | VLD / DC / RECONF / ICD / IPSJ-SLDM |
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| Conference Date | 2023/11/15(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Civic Auditorium Sears Home Yume Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2023 -New Field of VLSI Design- |
| Chair | Shigetoshi Nakatake(Univ. of Kitakyushu) / Tatsuhiro Tsuchiya(Osaka Univ.) / Yoshiki Yamaguchi(Tsukuba Univ.) / Makoto Ikeda(Univ. of Tokyo) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Yuichi Sakurai(Hitachi) / Toshinori Hosokawa(Nihon Univ.) / Yasushi Inoguchi(JAIST) / Tomonori Izumi(Ritsumeikan Univ.) / Hayato Wakabayashi(Sony Semiconductor Solutions) |
| Secretary | Yuichi Sakurai(Socionext) / Toshinori Hosokawa(Hirosaki Univ.) / Yasushi Inoguchi(Nihon Univ.) / Tomonori Izumi(Chiba Univ.) / Hayato Wakabayashi(NEC) / (Toyohashi Univ. of Tech.) |
| Assistant | Takuma Nishimoto(Hitachi) / / Yukitaka Takemura(INTEL) / Yasunori Osana(Kumamoto Univ.) / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Kumamoto University) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Special Interest Group on System and LSI Design Methodology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On Reducing Area Overhead of BIST for Approximate Multiplier Considering Truncated Bits |
| Sub Title (in English) | |
| Keyword(1) | BIST |
| Keyword(2) | approximate computing |
| Keyword(3) | multiplier |
| Keyword(4) | test cost reduction |
| 1st Author's Name | Daichi Akamatsu |
| 1st Author's Affiliation | Tokushima University(Tokushima Univ.) |
| 2nd Author's Name | Shougo Tokai |
| 2nd Author's Affiliation | Tokushima University(Tokushima Univ.) |
| 3rd Author's Name | Hiroyuki Yotsuyanagi |
| 3rd Author's Affiliation | Tokushima University(Tokushima Univ.) |
| 4th Author's Name | Masaki Hashizume |
| 4th Author's Affiliation | Tokushima University(Tokushima Univ.) |
| Date | 2023-11-16 |
| Paper # | VLD2023-60,ICD2023-68,DC2023-67,RECONF2023-63 |
| Volume (vol) | vol.123 |
| Number (no) | VLD-258,ICD-259,DC-260,RECONF-261 |
| Page | pp.pp.156-161(VLD), pp.156-161(ICD), pp.156-161(DC), pp.156-161(RECONF), |
| #Pages | 6 |
| Date of Issue | 2023-11-08 (VLD, ICD, DC, RECONF) |