| Presentation | 2023-10-11 Low power consumption of neural networks using memory bit reduction and sampling Hirokazu Kodachi, Masato Kitakami, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Advances in machine learning and the use of big data have increased the computational complexity of neural networks. As a result, the increase in power consumption of neural networks has become a problem. As a solution to this problem, we focused on the structure of neural networks. Neural networks have a structure in which features are distributed and propagated, so some errors can be tolerated. Therefore, there is a method to reduce the power consumption of neural network weights while maintaining recognition accuracy by reducing the mantissa part of the neural network weights that can tolerate bit errors. In this paper, we investigate the changes in power consumption and recognition accuracy by changing the data type of the memory used to store weights and reducing the data to be computed by sampling. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Neural Network / Low power consumption |
| Paper # | SS2023-26,DC2023-32 |
| Date of Issue | 2023-10-04 (SS, DC) |
| Conference Information | |
| Committee | SS / DC |
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| Conference Date | 2023/10/11(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Kozo Okano(Shinshu Univ.) / Tatsuhiro Tsuchiya(Osaka Univ.) |
| Vice Chair | Yoshiki Higo(Osaka Univ.) / Toshinori Hosokawa(Nihon Univ.) |
| Secretary | Yoshiki Higo(Shinshu Univ.) / Toshinori Hosokawa(Tokyo Inst. of Tech.) |
| Assistant | Shinsuke Matsumoto(Osaka Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Software Science / Technical Committee on Dependable Computing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low power consumption of neural networks using memory bit reduction and sampling |
| Sub Title (in English) | |
| Keyword(1) | Neural Network |
| Keyword(2) | Low power consumption |
| 1st Author's Name | Hirokazu Kodachi |
| 1st Author's Affiliation | Chiba University(Chiba Univ.) |
| 2nd Author's Name | Masato Kitakami |
| 2nd Author's Affiliation | Chiba University(Chiba Univ.) |
| Date | 2023-10-11 |
| Paper # | SS2023-26,DC2023-32 |
| Volume (vol) | vol.123 |
| Number (no) | SS-206,DC-207 |
| Page | pp.pp.27-31(SS), pp.27-31(DC), |
| #Pages | 5 |
| Date of Issue | 2023-10-04 (SS, DC) |