| Presentation | 2023-10-28 A design of ultra-low power reservoir computing system with analog CMOS spiking neural network circuits Satoshi Ono, Satoshi Moriya, Hideaki Yamamoto, Yasushi Yuminaka, Yoshihiko Horio, Shigeo Sato, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Spiking neural network (SNN) is expected to be applied to edge computing due to its low power consumption when implemented using event-driven circuits. In this study, we designed a reservoir computing system using SNN implemented with analog CMOS circuits operating in the subthreshold region[1]. We applied the design system to 10-digit speech recognition[2] and estimated its power consumption and accuracy by SPICE simulation. It was shown that the system could classify with 81.9% accuracy and consumed about 0.098 nJ per utterance for classification. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Spiking neural network / Reservoir computing / Analog CMOS circuits |
| Paper # | NC2023-29 |
| Date of Issue | 2023-10-20 (NC) |
| Conference Information | |
| Committee | NC / MBE |
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| Conference Date | 2023/10/27(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Tohoku Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | NC, ME |
| Chair | Hirokazu Tanaka(Tokyo City Univ.) / Hisashi Yoshida(Kinki Univ.) |
| Vice Chair | Jun Izawa(Univ. of Tsukub) / Akinori Ueno(Tokyo Denki Univ.) |
| Secretary | Jun Izawa(NTT) / Akinori Ueno(NAIST) |
| Assistant | Yoshimasa Tawatsuji(Waseda Univ.) / Takato Horii(Osaka Univ.) / Akihiko Tsukahara(Tokyo Denki Univ.) / Miki Kaneko(Osaka Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Neurocomputing / Technical Committee on ME and Bio Cybernetics |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A design of ultra-low power reservoir computing system with analog CMOS spiking neural network circuits |
| Sub Title (in English) | |
| Keyword(1) | Spiking neural network |
| Keyword(2) | Reservoir computing |
| Keyword(3) | Analog CMOS circuits |
| 1st Author's Name | Satoshi Ono |
| 1st Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 2nd Author's Name | Satoshi Moriya |
| 2nd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 3rd Author's Name | Hideaki Yamamoto |
| 3rd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 4th Author's Name | Yasushi Yuminaka |
| 4th Author's Affiliation | Gunma University(Gunma Univ.) |
| 5th Author's Name | Yoshihiko Horio |
| 5th Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 6th Author's Name | Shigeo Sato |
| 6th Author's Affiliation | Tohoku University(Tohoku Univ.) |
| Date | 2023-10-28 |
| Paper # | NC2023-29 |
| Volume (vol) | vol.123 |
| Number (no) | NC-233 |
| Page | pp.pp.23-23(NC), |
| #Pages | 1 |
| Date of Issue | 2023-10-20 (NC) |