| Presentation | 2023-10-06 A Design and Evaluation of the Up/Down Counter Type PWM Adder Using the Subthreshold Region Gaku Abe, Andrino Robles Roberto, Takumi Nihei, Tomochika Harada, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents the design and evaluation of a PWM adder circuit using up/down counters operating in the subthreshold region using 0.18μm CMOS technology. Previous research has designed PWM adder circuits using analog signals as input signals. This PWM adder has a circuit configuration that uses a delay circuit to convert an analog signal into a PWM signal and adds the signal. However, the circuit configuration relies on the process of converting analog input signals to PWM signals, resulting in a circuit configuration that requires two steps. Therefore, we redesign the PWM adder circuit using the PWM signal as the input signal. From the results, a simple PWM adder circuit with a reduced circuit scale can be realized. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Subthreshold Region / up/down counter / Pulse Width Modulation / Adder |
| Paper # | CAS2023-42,NLP2023-41 |
| Date of Issue | 2023-09-29 (CAS, NLP) |
| Conference Information | |
| Committee | NLP / CAS |
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| Conference Date | 2023/10/6(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Work plaza Gifu |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | CAS, NLP, etc. |
| Chair | Hiroyuki Torikai(Hosei Univ.) / Yasutoshi Aibara(OmniVision) |
| Vice Chair | Yuichi Tanji(Kagawa Univ.) / Norihiko Shinomiya(Soka Univ.) |
| Secretary | Yuichi Tanji(Gifu Univ.) / Norihiko Shinomiya(Chukyo Univ.) |
| Assistant | Yoshikazu Yamanaka(Utsunomiya Univ.) / Eri Ioka(Shibaura Inst. of Tech.) / Nao Ito(NIT, Toyama college) / Motoi Yamaguchi(TECHNOPRO) / Shinji Shimoda(Sony Semiconductor Solutions) / Shunsuke Koshita(Hachinohe Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Nonlinear Problems / Technical Committee on Circuits and Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Design and Evaluation of the Up/Down Counter Type PWM Adder Using the Subthreshold Region |
| Sub Title (in English) | |
| Keyword(1) | Subthreshold Region |
| Keyword(2) | up/down counter |
| Keyword(3) | Pulse Width Modulation |
| Keyword(4) | Adder |
| 1st Author's Name | Gaku Abe |
| 1st Author's Affiliation | Yamagata University(Yamagata Univ.) |
| 2nd Author's Name | Andrino Robles Roberto |
| 2nd Author's Affiliation | Yamagata University(Yamagata Univ.) |
| 3rd Author's Name | Takumi Nihei |
| 3rd Author's Affiliation | Yamagata University(Yamagata Univ.) |
| 4th Author's Name | Tomochika Harada |
| 4th Author's Affiliation | Yamagata University(Yamagata Univ.) |
| Date | 2023-10-06 |
| Paper # | CAS2023-42,NLP2023-41 |
| Volume (vol) | vol.123 |
| Number (no) | CAS-202,NLP-203 |
| Page | pp.pp.53-57(CAS), pp.53-57(NLP), |
| #Pages | 5 |
| Date of Issue | 2023-09-29 (CAS, NLP) |