| Presentation | 2023-08-08 In-Depth Timing Characterization of the Adiabatic Quantum-Flux-Parametron Logic Gate Yu Hoshika, Christopher L. Ayala, Nobuyuki Yoshikawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family and can operate at 5 GHz to 10 GHz with extremely low switching energy. We use digital simulation such as Verilog or SystemVerilog to design large-scale circuits using AQFP logic gates. Previous work on digital modeling used unconventional timing checks and timing characteristics of the AQFP logic gates were simplified. The intrinsic delays of the AQFP logic gate such as propagation and reset delay were not characterized deeply. To design large-scale circuits with GHz operating frequencies, a more in-depth timing characterization and more accurate timing model with industry-standard timing checks are needed. In this study, we investigated the appropriate timing definitions and new methods to evaluate the timing parameters of the AQFP logic gates for digital simulation. We observe new timing effects in the AQFP and determined how to properly consider them during characterization. We also consider a few approaches on how to realize the timing model and determined a candidate implementation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | adiabatic quantum-flux-parametron / AQFP / Josephson integrated circuits / gate-level-modeling / timing characterization |
| Paper # | SCE2023-9 |
| Date of Issue | 2023-08-01 (SCE) |
| Conference Information | |
| Committee | SCE |
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| Conference Date | 2023/8/8(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Yokohama National Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Shigehito Miki(NICT) |
| Vice Chair | |
| Secretary | (Kanazawa Inst. of Tech.) |
| Assistant | Hiroyuki Akaike(Daido Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Superconductive Electronics |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | In-Depth Timing Characterization of the Adiabatic Quantum-Flux-Parametron Logic Gate |
| Sub Title (in English) | |
| Keyword(1) | adiabatic quantum-flux-parametron |
| Keyword(2) | AQFP |
| Keyword(3) | Josephson integrated circuits |
| Keyword(4) | gate-level-modeling |
| Keyword(5) | timing characterization |
| 1st Author's Name | Yu Hoshika |
| 1st Author's Affiliation | Yokohama National University(YNU) |
| 2nd Author's Name | Christopher L. Ayala |
| 2nd Author's Affiliation | Institute of Advanced Sciences - Yokohama National University(IAS- YNU) |
| 3rd Author's Name | Nobuyuki Yoshikawa |
| 3rd Author's Affiliation | Yokohama National University(IAS - YNU) |
| Date | 2023-08-08 |
| Paper # | SCE2023-9 |
| Volume (vol) | vol.123 |
| Number (no) | SCE-153 |
| Page | pp.pp.45-48(SCE), |
| #Pages | 4 |
| Date of Issue | 2023-08-01 (SCE) |