| Presentation | 2023-08-02 A 1W/8R 20T SRAM Codebook for Deep Learning Processors to Reduce Main Memory Bandwidth Ryotaro Ohara, Masaya Kabuto, Masakazu Taichi, Atsushi Fukunaga, Yuto Yasuda, Riku Hamabe, Shintaro Izumi, Hiroshi Kawaguchi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We present a 1W8R 20T multi-port memory for codebook quantisation in deep learning processors, manufactured in a 40 nm process, achieving a memory read access time of 2.75 ns and power consumption of 2.7 pj/byte. In addition, simulations were performed based on the silicon results power obtained with the proposed memory, using NVIDIA's NVDLA deep learning processor as a motif. As a result, a reduction of 20.24% in power consumption and 26.24% in area was achieved. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Codebook / multiport memory / deep neural network |
| Paper # | SDM2023-44,ICD2023-23 |
| Date of Issue | 2023-07-25 (SDM, ICD) |
| Conference Information | |
| Committee | SDM / ICD / ITE-IST |
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| Conference Date | 2023/8/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hokkaido Univ. Multimedia Education Bldg. 3F |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
| Chair | Shunichiro Ohmi(Tokyo Inst. of Tech.) / Makoto Ikeda(Univ. of Tokyo) / Masayuki Ikebe(Hokkaido Univ.) |
| Vice Chair | Tatsuya Usami(Rapidus) / Hayato Wakabayashi(Sony Semiconductor Solutions) / Takashi Komuro(Saitama Univ.) / Kazuhiro Shimonomura(Ritsmeikan Univ.) / Keiichiro Kagawa(Shizuoka Univ.) |
| Secretary | Tatsuya Usami(Tohoku Univ.) / Hayato Wakabayashi(Panasonic) / Takashi Komuro(Kioxia) / Kazuhiro Shimonomura(Shinshu Univ.) / Keiichiro Kagawa(Tokyo Inst. of Tech.) |
| Assistant | Takuji Hosoi(Kwansei Gakuin Univ.) / Takuya Futase(Western Digital) / Ryo Shirai(Kyoto Univ.) / Jun Shiomi(Osaka Univ.) / Takeshi Kuboki(Sony Semiconductor Solutions) / Junichi Akita(Kanazawa Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials / Technical Committee on Integrated Circuits and Devices / Technical Group on Information Sensing Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 1W/8R 20T SRAM Codebook for Deep Learning Processors to Reduce Main Memory Bandwidth |
| Sub Title (in English) | |
| Keyword(1) | Codebook |
| Keyword(2) | multiport memory |
| Keyword(3) | deep neural network |
| 1st Author's Name | Ryotaro Ohara |
| 1st Author's Affiliation | Kobe University(Kobe Univ) |
| 2nd Author's Name | Masaya Kabuto |
| 2nd Author's Affiliation | Kobe University(Kobe Univ) |
| 3rd Author's Name | Masakazu Taichi |
| 3rd Author's Affiliation | Kobe University(Kobe Univ) |
| 4th Author's Name | Atsushi Fukunaga |
| 4th Author's Affiliation | Kobe University(Kobe Univ) |
| 5th Author's Name | Yuto Yasuda |
| 5th Author's Affiliation | Kobe University(Kobe Univ) |
| 6th Author's Name | Riku Hamabe |
| 6th Author's Affiliation | Kobe University(Kobe Univ) |
| 7th Author's Name | Shintaro Izumi |
| 7th Author's Affiliation | Kobe University(Kobe Univ) |
| 8th Author's Name | Hiroshi Kawaguchi |
| 8th Author's Affiliation | Kobe University(Kobe Univ) |
| Date | 2023-08-02 |
| Paper # | SDM2023-44,ICD2023-23 |
| Volume (vol) | vol.123 |
| Number (no) | SDM-143,ICD-144 |
| Page | pp.pp.41-44(SDM), pp.41-44(ICD), |
| #Pages | 4 |
| Date of Issue | 2023-07-25 (SDM, ICD) |