Presentation 2023-07-06
Lifetime improvement of Memristor-based Hyperdimensional Computing Inference Accelerator by Error Detection and Built-in Self Repair
Tetsuro Iwasaki, Michihiro Shintani,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) The implementation of hyperdimensional computing in memristors is expected to realize a highly efficient inferencer for edge computing, which processes various cognitive tasks in a lightweight manner by mapping them onto hyperdimensional vectors of thousands to tens of thousands of dimensions. On the other hand, it has been pointed out that memristors have a long-term reliability issue compared to silicon materials, it is thus essential to design for high reliability. This paper proposes a design method for the memristor HDC inference accelerator to extend its lifetime. More specifically, we perform error detection and redundancy relief by replacing the detected faulty memristor cells with redundant cells by performing a normalized checksum of the hyper-dimensional vectors obtained by inference queries. We conducted numerical experiments to confirm the effectiveness of the proposed method using a language recognition task. The experimental results show that the proposed method can increase the device lifetime by 5 times while maintaining the recognition accuracy compared to the case where no reliability-aware design is applied.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Hyperdimensional Computing / Memristor / Dependability-aware design / Built-in self repair
Paper # CAS2023-5,VLD2023-5,SIP2023-21,MSS2023-5
Date of Issue 2023-06-29 (CAS, VLD, SIP, MSS)

Conference Information
Committee MSS / CAS / SIP / VLD
Conference Date 2023/7/6(2days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Shingo Yamaguchi(Yamaguchi Univ.) / Yasutoshi Aibara(OmniVision) / Takayuki Nakachi(Ryukyu Univ.) / Shigetoshi Nakatake(Univ. of Kitakyushu)
Vice Chair Toshiyuki Miyamoto(Osaka Inst. of Tech.) / Norihiko Shinomiya(Soka Univ.) / Koichi Ichige(Yokohama National Univ.) / Kiyoshi Nishikawa(okyo Metropolitan Univ.) / Yuichi Sakurai(Hitachi)
Secretary Toshiyuki Miyamoto(Osaka Univ.) / Norihiko Shinomiya(NEC) / Koichi Ichige(Soka Univ.) / Kiyoshi Nishikawa(Renesas Electronics) / Yuichi Sakurai(Chiba Univ.)
Assistant Masato Shirai(Shimane Univ.) / Nao Ito(NIT, Toyama college) / Motoi Yamaguchi(TECHNOPRO) / Shinji Shimoda(Sony Semiconductor Solutions) / Shunsuke Koshita(Hachinohe Inst. of Tech.) / Taichi Yoshida(UEC) / Sayaka Shiota(Tokyo Metropolitan Univ.) / Takuma Nishimoto(Hitachi)

Paper Information
Registration To Technical Committee on Mathematical Systems Science and its Applications / Technical Committee on Circuits and Systems / Technical Committee on Signal Processing / Technical Committee on VLSI Design Technologies
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Lifetime improvement of Memristor-based Hyperdimensional Computing Inference Accelerator by Error Detection and Built-in Self Repair
Sub Title (in English)
Keyword(1) Hyperdimensional Computing
Keyword(2) Memristor
Keyword(3) Dependability-aware design
Keyword(4) Built-in self repair
Keyword(5)
1st Author's Name Tetsuro Iwasaki
1st Author's Affiliation Kyoto Institute of Technology(KIT)
2nd Author's Name Michihiro Shintani
2nd Author's Affiliation Kyoto Institute of Technology(KIT)
Date 2023-07-06
Paper # CAS2023-5,VLD2023-5,SIP2023-21,MSS2023-5
Volume (vol) vol.123
Number (no) CAS-97,VLD-98,SIP-99,MSS-100
Page pp.pp.22-27(CAS), pp.22-27(VLD), pp.22-27(SIP), pp.22-27(MSS),
#Pages 6
Date of Issue 2023-06-29 (CAS, VLD, SIP, MSS)