| Presentation | 2023-07-06 Performance Improvement by Memory access and Process-level Pipelining for High-level Synthesized Sprite Drawing Hardware Yuka Otani, Akira Yamawaki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A mobile terminal with hardware reconfigurability can achieve higher performance and lower power consumption by performing the high computational task as a hardware module. This paper develops an optimized software of 2D sprite drawing for high-level synthesis, HLS, to realize a game application on the proposed mobile terminal. The HLS can convert automatically from software to hardware module. A software description method is proposed to make the HLS generate a well-organized hardware module. Our proposal loads the sprite and background images simultaneously from the memory while compositing them. Then, the composited results are stored into the memory. In addition, the former and latter processes are overlapped. Experimental results measured on a real machine show that our high-level synthesized hardware can achieve a performance improvement of 1.6 times and a power efficiency of 16 times compared with a software execution. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High-Level Synthesis (HLS) / Sprite / Drawing / Game library / FPGA / Software / Hardware |
| Paper # | CAS2023-3,VLD2023-3,SIP2023-19,MSS2023-3 |
| Date of Issue | 2023-06-29 (CAS, VLD, SIP, MSS) |
| Conference Information | |
| Committee | MSS / CAS / SIP / VLD |
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| Conference Date | 2023/7/6(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Shingo Yamaguchi(Yamaguchi Univ.) / Yasutoshi Aibara(OmniVision) / Takayuki Nakachi(Ryukyu Univ.) / Shigetoshi Nakatake(Univ. of Kitakyushu) |
| Vice Chair | Toshiyuki Miyamoto(Osaka Inst. of Tech.) / Norihiko Shinomiya(Soka Univ.) / Koichi Ichige(Yokohama National Univ.) / Kiyoshi Nishikawa(okyo Metropolitan Univ.) / Yuichi Sakurai(Hitachi) |
| Secretary | Toshiyuki Miyamoto(Osaka Univ.) / Norihiko Shinomiya(NEC) / Koichi Ichige(Soka Univ.) / Kiyoshi Nishikawa(Renesas Electronics) / Yuichi Sakurai(Chiba Univ.) |
| Assistant | Masato Shirai(Shimane Univ.) / Nao Ito(NIT, Toyama college) / Motoi Yamaguchi(TECHNOPRO) / Shinji Shimoda(Sony Semiconductor Solutions) / Shunsuke Koshita(Hachinohe Inst. of Tech.) / Taichi Yoshida(UEC) / Sayaka Shiota(Tokyo Metropolitan Univ.) / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Mathematical Systems Science and its Applications / Technical Committee on Circuits and Systems / Technical Committee on Signal Processing / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance Improvement by Memory access and Process-level Pipelining for High-level Synthesized Sprite Drawing Hardware |
| Sub Title (in English) | |
| Keyword(1) | High-Level Synthesis (HLS) |
| Keyword(2) | Sprite |
| Keyword(3) | Drawing |
| Keyword(4) | Game library |
| Keyword(5) | FPGA |
| Keyword(6) | Software |
| Keyword(7) | Hardware |
| 1st Author's Name | Yuka Otani |
| 1st Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 2nd Author's Name | Akira Yamawaki |
| 2nd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| Date | 2023-07-06 |
| Paper # | CAS2023-3,VLD2023-3,SIP2023-19,MSS2023-3 |
| Volume (vol) | vol.123 |
| Number (no) | CAS-97,VLD-98,SIP-99,MSS-100 |
| Page | pp.pp.10-15(CAS), pp.10-15(VLD), pp.10-15(SIP), pp.10-15(MSS), |
| #Pages | 6 |
| Date of Issue | 2023-06-29 (CAS, VLD, SIP, MSS) |